Dr. Robin Khosla, Ph.D.

The Tunnel Field Effect Transistor (TFET) often suffers from low ON current (ION), charge traps, and thermal variability, which limits its performance and reliability. To address these issues, the source work function engineered Ge Charge Plasma Double Gate Tunnel Field Effect Transistor(CPDGTFET) device structure with HfO2/Al2O3 bilayer gate dielectric is designed and investigated using numerical TCAD simulations. The proposed Ti/HfO2/Al2O3/Ge CP-DGTFET device structure showed excellent DC characteristics with exceptional ION, ION/IOFF ratio, and minimal sub-threshold swing (S) of∼3.04 × 1E−4A μm−1 ,∼1.2 × 1E10, and∼3.4 mV/dec, respectively. Furthermore, the device’s analog characteristics displayed good transconductance, cut-off frequency, and gain bandwidth product of∼0.75 mS/μm,∼0.97 THz, and∼102 GHz, respectively. Moreover, the charge trap exploration divulges that positive ITCs can enhance device performance, whereas negative ITCs can adversely impact the electrical characteristics of CP-DGTFET. Additionally, the temperature dependent analysis showed that the OFF-state leakage current increases from ∼1.7 × 1E−15 A μm−1 to 2.4 × 1E−10A μm−1 with temperature fluctuations from 275 K to 375 K. Overall, the work functionengineered CP-based Ti/HfO2/Al2O3/Ge DGTFET device structure shows great potential for improving the performance and reliability of Ge TFET technology. For details view doi: 10.1088/2631-8695/ad3c14 

The device reliability on account of charge traps at the Al2O3/Ge interface is a main distress for the Ge-based Tunnel Field Effect Transistor (TFET). Here, the influence of Interface Trap Charges (ITC) on the charge plasma-based Ge-Double-Gate TFET (CP-Ge-DGTFET) and conventional Ge-DGTFET's DC, Analog/RF, and linearity characteristics have been inspected using technology-computer-aided-design (TCAD) simulations for the donor (positive) and acceptor (negative) ITC. The charge plasma concept is adopted to induce excess carrier concentration within the source region on the integration of optimum work function metal electrodes. To recognize the impact of ITC, several figures of merits have been investigated, such as transfer characteristics, electric field, transconductance, cut-off frequency, parasitic capacitance, and linearity performance parameters (VIP2, VIP3, IIP3, and IMD3). The CP-Ge-DGTFET device structure revealed superior performance and reliability in comparison to Ge-DGTFET, even under the influence of ITC at the Al2O3/Ge interface. Therefore, the CP-Ge-DGTFET device structure is a sturdy contender for Analog/RF and low-power switching applications. For details view doi:10.1016/j.microrel.2023.115312

Here, Ge-Vertical Tunnel FET (VTFET)'s DC, Analog, and Linearity performance is investigated with variation in transistor regions doping, doping gradient step size, interface trap charges (ITC), and temperature. The CMOS Compatible and fabrication feasible Ge-VTFET with drain doping gradient revealed good performance and reliability even under ITC and temperature deviations, suitable for low-power switching & analog applications. For details view doi:10.1016/j.mseb.2023.116996 

Here, we present the design of a FASnI3 active layer-based PSC with Nickel oxide (NiO) as Hole Transport Layer (HTL) & Zinc Oxy-Sulphide (ZnO0.25S0.75) as the Electron Transport Layer (ETL). The proposed Au/NiO/FASnI3/ZnO0.25S0.75/FTO, device structure is investigated using SCAPS-1D solar cell capacitance simulator. The performance parameters of proposed solar cells device structure are investigated with variations in active layer (FASnI3) thickness, defect density & doping concentration; and variations of NiO HTL & ZnO0.25S0.75 ETL thickness, electron affinity & doping concentration to obtain higher performance. Moreover, the influence of series & shunt resistance, and temperature on the performance parameters of proposed solar cell device structure is inspected for lead-free and eco-friendly solar cell device applications. For details view doi: https://doi.org/10.1016/j.rio.2023.100444 

There are indelible challenges related to transistor action and realization of emerging two-dimensional van der Waals (vdW) multilayer (2D ml) field-effect transistors (FETs), to the post silicon technology era. For scalability, a cost-effective large area ultrafine thin films interface and band alignment of multilayer channel material with compatible gate dielectric are essential. Here, 2D ml hafnium disulfide (HfS 2) and ZrO 2 are employed as channel material and gate dielectric, respectively, and anticipated that vdW interaction of said structures entails the high-quality interface with trivial dangling bonds and defects caused by lattice mismatch. The investigated Al/ZrO 2 /HfS 2 /Al μ-IDE FETs exhibit the subthreshold swing (SS) ∼ 65 mV/dec, Ion/Ioff ratio of ∼ 1E4, transconductance of ∼ 3.99 μ S, effective mobility of ∼ 74 cm 2 /Vs at Vgs of 2 V, and leakage current density of ∼ 33.8 nA/cm 2 at Vgs of − 1 V. Thus, the steep SS, sturdy current saturation, low-voltage operation ( ∼ 3 V), and leakage current establish the potential candidature of HfS 2 and ZrO 2 -based 2-D FETs for both conventional and ubiquitous electronics. For details view doi: 10.1109/TED.2022.3202510

Here, we present the first ever report on the authoritative integration of ferroelectric (FE) hafnium zirconium oxide (HZO) over the p-Ge/n-Ge −on−n -Si system. A rudimentary approach for the carrier modulation in the channel was employed using depletion approximation and negative capacitance (NC) to fabricate HZO and thin p-Ge channel-based FET. The TaN/HZO/TaN stacks were optimized and characterized for enhanced ferroelectricity and non-centrosymmetric orthorhombic phase, which is further confirmed with piezoresponse force microscopic (PFM) analysis. The trivial loop hysteresis conditions to validate the NCFET operation was discussed. The devices demonstrated a lower subthreshold swing (SS) of ~23.44 mV/dec and ION/IOFF ratio of 10 5 . The threshold voltage shift Vt=−0.6 and −1.1 V with the body bias voltage of 0.25 and 0.5 V, respectively. Minimum DIBL measured ~26 mV/V, and rule-out gate induces drain lowering (GIDL) effect due to no gate–drain region overlap. For details view doi: 10.1109/TED.2022.3161857

This Letter reports Pt/SBT/La2O3/Si, MFIS structures for nonvolatile memory applications. Here SBT is used as a ferroelectric layer due to its expected better endurance & thermal stability than PZT counterparts and La2O3 is used as a superior buffer layer due to its expected better leakage characteristics. The crystallinity of SBT thin films is analyzed using grazing incidence x-ray diffraction (GIXRD) to confirm the ferroelectric phase of SBT. The surface topography of La2O3 and SBT thin films is evaluated using atomic force microscopy (AFM). The electrical characteristics, i.e., memory, data retention, and leakage characteristics, along with the current conduction mechanism, at 300K, are systematically investigated using capacitance–voltage (C–V), capacitance–time (C–T), and current–voltage (I–V) measurements, respectively. Additionally, the ferroelectricity of SBT is confirmed through pulse current– time (I–T) measurements of the Pt/SBT/Pt, Metal/Ferroelectric/Metal (MFM) system. Also, the quality of the buffer layer is validated in Pt/La2O3/Si, Metal/Oxide/Semiconductor (MOS) structures using the C–V and I–V measurements. For details view, DOI: 10.1063/5.0055792

In this review, we cover numerous advances and various important reports on integrating ferroelectric materials for different electronic device applications to give a broad picture, perspectives, projections, comparisons, and discussions, especially for those intending to work on ferroelectric materials, high-speed semiconductor computing/logic devices, and emerging nonvolatile ferroelectric memories. The explanations are kept straightforward from a newbie perspective to relate to the real-world application while also covering the recent advances in the field. For details view, DOI: https://doi.org/10.1021/acsaelm.0c00851

Here, we demonstrate a complete process development of high-quality remote plasma-enhanced atomic layer deposition (Re-PEALD) of Al2O3 thin films for a wide temperature range from ∼100 to 300 deg Celcius suitable for various nanoelectronics applications ranging from flexible substrates to low thermal budget and high mobility alternate semiconductor substrates. For details view, DOI: https://doi.org/10.1016/j.sse.2021.108027

Here, we demonstrate a maskless lithography approach to SU-8 based sensitive and high-g Z-axis polymer MEMS accelerometers using serpentine spring structures suitable for navigation, space, and medical applications, using simulation and experimental methods. Thanks to the collaborative efforts of colleagues at IIT Mandi. For details view, DOI: https://doi.org/10.1007/s00542-021-05217-0

Our recent work on Charge trapping investigation of Al/HfO2/epi-Ge on cost-effective Si substrates using nanoscopic KPFM techniques is available online on IEEE Transaction of Nanotechnology. Thanks to the collaborative works of the team at IIT Mandi and the University of Stuttgart. For details view, doi: 10.1109/TNANO.2021.3069820.