Enhancement mode GaN-based high electron mobility transistors are crucial for power electronics switching applications. The heavily Mg-doped pGaN region pulls Fermi energy towards its valence band, depleting the two-dimensional electron gas (2DEG) region. This p-doping primarily leads to traps in the AlGaN barrier, leading to gate current through trap-assisted tunneling (TAT). We show that the gate current and threshold voltage need to be tuned together for the desired performance of the enhancement mode transistors. 

Improved performance of diamond-based pMOS transistors with a combination of p-type Nickel Oxide and n-type Indium Tin Oxide (NiOX/ITO) reverse bias diode as the gate dielectric is demonstrated. The device shows negative threshold voltage, improved subthreshold slope, higher current ON/OFF ratio, and peak gate leakage current reduction, all of which are explained in a common framework using energy band diagram.

The device characteristics of AlGaAs/GaAs light-emitting transistors with single and double quantum wells in the base were modeled and calibrated in Silvaco TCAD, validating the results against experimental data at different temperatures. A modified charge control model was also developed by incorporating the tunneling lifetime of carriers in the quantum well region, enhancing the accuracy of device performance predictions.

A unified model was developed for the transfer characteristics, output characteristics, temperature dependency, breakdown characteristics, off-state capacitances, gate capacitance, and off-state leakage of pGaN high-electron-mobility transistors (HEMTs) using Sentaurus TCAD. The model incorporates mechanisms such as trap-assisted tunneling, direct tunneling, field plate leakage, leakage through carbon-doped GaN, substrate leakage via thermionic emission from AlN/Si, and band-to-band tunneling. Calibration was performed using experimental data from devices with various field plate designs and gate stacks. Additionally, the model is being extended to simulate and calibrate the dynamic on-resistance and pulsed I-V behavior of the device, including pre- and post-stress measurements under different stress voltages and temperatures.

Back-gated and dual-gated Indium Tin Oxide channel MOSFETs were modeled for use as memory access transistors in HfO₂-based resistive random-access memory (RRAM) for monolithic 3D embedded memory integration of 1T-1R RRAM cells. Various compact models for thin-film transistors, including the BSIM model commonly used for silicon MOSFETs, were analyzed. A modified BSIM compact model was implemented for dual-gate thin-film transistors, and a positive bias temperature instability (PBTI) model is also being incorporated. The model is being calibrated with experimental data from devices featuring different channel lengths and metal work functions.