Crypto-Genome Signature for Securing Hardware Accelerators
Designing Low-Cost Reliable and Security Aware Hardware Accelerators
Designing Optimized and Secured Reusable Convolutional Hardware Accelerator
Fault Secured JPEG-Codec Hardware Accelerator design
High-level Synthesis based Hardware Accelerator Design for CNN Applications
Protecting Trojan Secured DSP cores against IP piracy using Facial Biometrics
Securing Fault-Detectable CNN Hardware Accelerator
Securing Reusable Hardware IP cores using Palmprint Biometric
Security-Desig cost Tradeoff for Low-cost Hardware Design
Swarm Intelligence Driven ESL Synthesis for Functional Trojan Fortification
Symmetrical Hardware IP protection