A. Sengupta, R. Chaurasia and T. Reddy, “Contact-Less Palmprint Biometric for Securing DSP Coprocessors Used in CE Systems,” IEEE Trans. Consum. Electron., vol. 67, no. 3, pp. 202-213, Aug. 2021, doi: 10.1109/TCE.2021.3105113. (Impact Factor: 10.9)

A. Sengupta and R. Chaurasia, “Secured Convolutional Layer IP Core in Convolutional Neural Network Using Facial Biometric,” IEEE Trans. Consum. Electron., vol. 68, no. 3, pp. 291-306, Aug. 2022, doi: 10.1109/TCE.2022.3190069. (Impact Factor: 10.9)

R. Chaurasia and A. Sengupta, “Retinal Biometric for Securing JPEG-Codec Hardware IP core for CE systems,” IEEE Trans. Consum. Electron., vol. 69, no. 3, pp. 441-457, Aug. 2023, doi: 10.1109/TCE.2023.3264669. (Impact Factor: 10.9)

A. Sengupta, R. Chaurasia and A. Anshul, “Robust Security of Hardware Accelerators using Protein Molecular Biometric Signature and Facial Biometric Encryption Key,” IEEE Trans. Very Large Scale Integr. (VLSI) Syst., vol. 31, no. 6, pp. 826-839, June 2023, doi: 10.1109/TVLSI.2023.3265559. (Impact Factor: 3.1)

M. Rathor, A. Sengupta, R. Chaurasia and A. Anshul “Exploring Handwritten Signature Image Features for Hardware Security,” IEEE Trans. Dependable Secure Comput. (TDSC), vol. 20, no. 5, pp. 3687-3698, 1 Sept.-Oct. 2023, doi: 10.1109/TDSC.2022.3218506. (Impact Factor: 7.5)

A. Sengupta and R. Chaurasia, “Securing IP Cores for DSP Applications Using Structural Obfuscation and Chromosomal DNA Impression,” IEEE Access, vol. 10, pp. 50903-50913, 2022, doi: 10.1109/ACCESS.2022.3174349. (Impact Factor: 3.6)

R. Chaurasia, A. Anshul, A. Sengupta and S. Gupta, “Palmprint Biometric Versus Encrypted Hash Based Digital Signature for Securing DSP Cores Used in CE Systems,” IEEE Consum. Electron. Mag. (CEM), vol. 11, no. 5, pp. 73-80, 1 Sept. 2022, doi: 10.1109/MCE.2022.3153276. (Impact Factor: 4.5)

A. Sengupta and R. Chaurasia, “Secure FFT IP using C-way Partitioning-based Obfuscation and Fingerprint,” IEEE Design & Test, Accepted April 2024. (Impact Factor: 2)

M. Rathor, A. Anshul, K. Bharath, R. Chaurasia and A. Sengupta “Quadruple Phase Watermarking during High Level Synthesis for Securing Reusable Hardware IP Cores”, “Elsevier Journal Comput. Electr. Eng.”, vol. 105, 2023, doi.org/10.1016/j.compeleceng.2022.108476. (Impact Factor: 4.152)

R. Chaurasia and A. Sengupta, “Multi-cut based architectural obfuscation and handprint biometric signature for securing transient fault detectable IP cores during HLS,” Integr. VLSI J, Vol. 95, 2023,102114,ISSN 0167-9260, doi:10.1016/j.vlsi.2023.102114. (Impact Factor: 1.9)

A. Sengupta, M. Rathor and R. Chaurasia, “Biometrics for Hardware Security and Trust: Discussion and Analysis,” IT Professional, vol. 25, no. 4, pp. 36-44, July-Aug. 2023, doi: 10.1109/MITP.2023.3277594. (Impact Factor: 2.6)

A. Sengupta, R. Chaurasia and M. Rathor, “HLS based Swarm Intelligence Driven Optimized Hardware IP Core for Linear Regression based Machine Learning,” IET J. Eng., Volume: 2023, Issue: 8, August 2023, e12299.

A. Sengupta, R. Chaurasia and K Bharath, “Exploring unified biometrics with encoded dictionary for hardware security of fault secured IP core designs,” Elsevier Journal Comput. Electr. Eng., Volume 111, Part A, 2023, 108928. (Impact Factor: 4.3)

A. Sengupta, A. Anshul, R. Chaurasia, “Exploration of Optimal Functional Trojan-Resistant Hardware Intellectual Property (IP) Core Designs during High Level Synthesis”, Microprocessors and Microsystems, Volume 103, 2023, 104973. (Impact Factor: 3.503)

R. Chaurasia and A. Sengupta "Exploiting Retina Biometric Fused with Encoded Hash for Designing Watermarked Convolutional Hardware IP against Piracy", Springer Nature Computer Science, Invited paper, Accepted, 2024.

A. Sengupta and Rahul Chaurasia "Secure implantable cardiac pacemaker for medical consumer electronics", npj Biomed. Innov. 2, 5 (2025). https://doi.org/10.1038/s44385-025-00008-y.

Rahul Chaurasia, Anirban Sengupta, "Secure Accelerated Computing: High-Level Synthesis Based Hardware Accelerator Design for CNN Applications," 2024 IEEE International Symposium on Smart Electronic Systems (iSES), New Delhi, India, 2024, pp. 122-127, doi: 10.1109/iSES63344.2024.00034.

Anirban Sengupta, Rahul Chaurasia "SWIFT: Swarm Intelligence Driven ESL Synthesis for Functional Trojan Fortification," 2024 IEEE International Symposium on Smart Electronic Systems (iSES), New Delhi, India, 2024, pp. 116-121, doi: 10.1109/iSES63344.2024.00033.

R. Chaurasia and A. Sengupta, “Securing Reusable Hardware IP cores using Palmprint Biometric,” 2021 IEEE International Symposium on Smart Electronic Systems (iSES), Jaipur, India, 2021, pp. 410-413, doi: 10.1109/iSES52644.2021.00099.

R. Chaurasia and A. Sengupta, “Crypto-Genome Signature for Securing Hardware Accelerators,” 2022 IEEE 19th India Council International Conference (INDICON), Kochi, India, 2022, pp. 1-6, doi: 10.1109/INDICON56171.2022.10039955.

R. Chaurasia and A. Sengupta, “Protecting Trojan Secured DSP cores against IP piracy using Facial Biometrics,” 2022 IEEE 19th India Council International Conference (INDICON), Kochi, India, 2022, pp. 1-6, doi: 10.1109/INDICON56171.2022.10039864.

R. Chaurasia and A. Sengupta, “Security Vs Design Cost of Signature Driven Security Methodologies for Reusable Hardware IP Core,” 2022 IEEE International Symposium on Smart Electronic Systems (iSES), Warangal, India, 2022, pp. 283-288, doi: 10.1109/iSES54909.2022.00064.

R. Chaurasia and A. Sengupta, “Symmetrical Protection of Ownership Right's for IP Buyer and IP Vendor using Facial Biometric Pairing,” 2022 IEEE International Symposium on Smart Electronic Systems (iSES), Warangal, India, 2022, pp. 272-277, doi: 10.1109/iSES54909.2022.00062. 

R. Chaurasia, A. Reddy Asireddy and A. Sengupta, “Fault Secured JPEG-Codec Hardware Accelerator with Piracy Detective Control using Secure Fingerprint Template,” 2023 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), Juan-Les-Pins, France, 2023, pp. 1-6, doi: 10.1109/DFT59622.2023.10313536.

R. Chaurasia, A. Sengupta “Designing Optimized and Secured Reusable Convolutional Hardware Accelerator Against IP Piracy Using Retina Biometrics”, 2023 IEEE International Symposium on Smart Electronic Systems (iSES), Ahmedabad, India, 2023, pp. 153-158, doi: 10.1109/iSES58672.2023.00040.

A. Sengupta, R. Chaurasia, and A. Anshul, “Hardware Security of Digital Image Filter IP Cores against Piracy using IP Seller’s Fingerprint Encrypted Amino Acid Biometric Sample,” 2023 Asian Hardware Oriented Security and Trust Symposium (AsianHOST), Tianjin, China, 2023, pp. 1-6, doi: 10.1109/AsianHOST59942.2023.10409476.

A. Sengupta, R. Chaurasia “Securing Fault-Detectable CNN Hardware Accelerator Against False Claim of IP Ownership Using Embedded Fingerprint as Countermeasure”, 2023 IEEE International Symposium on Smart Electronic Systems (iSES), Ahmedabad, India, 2023 pp. 147-152, doi: 10.1109/iSES58672.2023.00039.

R. Chaurasia "SecureHD: Designing Low-Cost Reliable and Security Aware Hardware Accelerators During High-Level Synthesis for Computationally Intensive Application Frameworks," 2024 IEEE International Symposium on Smart Electronic Systems (iSES), New Delhi, India, 2024, pp. 380-383, doi: 10.1109/iSES63344.2024.00086.

R. Chaurasia “HLS based Hardware Security and IP Protection,” 37th International Conference on VLSI Design (VLSID)- SRF, Kolkata, India (VLSID, 2024), Accepted, Dec 2023.

Vishal Chourasia, Anirban Sengupta, Rahul Chaurasia "HLS Based Hardware Watermarking of Blur, Embossment and Sharpening Filters Using Fused Ocular Biometrics and Digital Signature", 37th IEEE International System-on-Chip Conference (SOCC), Dresden, Germany, Accepted, 2024.

U. K. Sahu, A. Jain, R. Chaurasia and K. K. Hiran, “Blockchain based Pharmaceutical Supply Chain and its Challenges: A Review and Proposed Solution,” 2023 IEEE International Conference on ICT in Business Industry & Government (ICTBIG), Indore, India, 2023, pp. 1-5, doi: 10.1109/ICTBIG59752.2023.10456151.

R. Chaurasia, A. Sengupta, P. Pradeeprao “Secured Integrated Circuit (IC/IP) Design Flow”, CRC Book "Nanoelectronics for Next-generation Integrated Circuits", 2022, eBook ISBN9781003155751.

A. Sengupta and R. Chaurasia “Hardware IP Cores for Image Processing Functions”, IOP Book “Advances in Image and Data Processing using VLSI Design", 2022, pp. 7.1 - 7.14, doi: 10.1088/978-0-7503-3919-3ch7.

A. Sengupta and R. Chaurasia “Integrated Defense using Structural obfuscation and Encrypted DNA based Biometric for Hardware Security,” IET Book “Physical Biometrics for Hardware Security of DSP and Machine Learning Coprocessors,” 2023, Chap. 2, pp. 25-56, doi: 10.1049/PBCS080E_ch2.

A. Sengupta and R. Chaurasia “Facial Signature based Biometrics for Hardware Security and IP Core protection,” IET Book "Physical Biometrics for Hardware Security of DSP and Machine Learning Coprocessors", 2023, Chap. 3, pp. 57-92, doi: 10.1049/PBCS080E_ch3.

A. Sengupta and R. Chaurasia “Secured Convolutional Layer Hardware Co-processor in Convolutional Neural Network (CNN) using Facial Biometric,” IET Book "Physical Biometrics for Hardware Security of DSP and Machine Learning Coprocessors", 2023, Chap. 4, pp. 93-146, doi: 10.1049/PBCS080E_ch4.

A. Sengupta and R. Chaurasia “Handling Symmetrical IP Core Protection and IP Protection (IPP) of Trojan Secured Designs in HLS using Physical Biometrics,” IET Book "Physical Biometrics for Hardware Security of DSP and Machine Learning Coprocessors", 2023, Chap. 5, pp. 147-198, doi: 10.1049/PBCS080E_ch5.

A. Sengupta and R. Chaurasia “Methodology for Exploration of Security-Design Cost Tradeoff for Signature-based Security Algorithms,” IET Book "Physical Biometrics for Hardware Security of DSP and Machine Learning Coprocessors", 2023, Chap. 8, pp. 259-297, doi: 10.1049/PBCS080E_ch8.

A. Anshul, R. Chaurasia and A. Sengupta “Securing Hardware Coprocessors against Piracy using Biometrics for Secured IoT systems,” IET Book “Artificial Intelligence for Biometrics and Cybersecurity”, 2023, Chap. 8, pp.175-193, doi:10.1049/PBSE020E_ch8.

A. Sengupta and R. Chaurasia “Introduction to High-Level Synthesis based Hardware Security and Trust: Goals and Challenges,” IET Book “High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection”, 2024, Chap. 1, Accepted April 2024.

A. Sengupta and R. Chaurasia “High-Level Synthesis based Methodology for Securing Hardware IPs using Retinal Biometrics,” IET Book “High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection”, 2024, Chap. 3, Accepted April 2024.

A. Sengupta and R. Chaurasia “Hardware Obfuscation -High level Synthesis based Structural Obfuscation for Hardware Security and Trust,” IET Book “High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection”, 2024, Chap. 8, Accepted April 2024.

A. Sengupta and R. Chaurasia “Hardware Obfuscation-Algorithmic Transformation based Obfuscation for Secure Floorplan Driven High Level Synthesis,” IET Book “High-Level Synthesis based Methodologies for Hardware Security, Trust and IP Protection”, 2024, Chap. 9, Accepted April 2024.

Rahul Chaurasia, Anirban Sengupta, “IP Core Protection and Detective Control of Data Intensive Hardware IPs against Piracy,” Doctor of Philosophy Thesis, Indian Institute of Technology Indore, 2023.

Rahul Chaurasia, Anirban Sengupta, “SOFTDEEP: HLS based IP Protection tool for Secure Optimal Fault Tolerant Designs with Embedded Encrypted Protein signature,” Post-Doc Translational Research, Indian Institute of Technology Indore, 2024.