Rahul Chaurasia

Rahul Chaurasia, M'IEEE, CTSoc, CS, CASS

Assistant Professor

Department of Computer Science & Engineering ,

Indian Institute of Information Technology Bhopal-462003, India.

Email: rchaurasia179[at]gmail[dot]com; rahulchaurasia[at]iiitbhopal[dot]ac[dot]in

Google Scholar

DBLP

Web of Science

About:

I completed Ph.D. in August 2023, titled "IP Core Protection and Detective Control of Data-intensive Hardware IPs against Piracy," at the Department of Computer Science & Engineering, Indian Institute of Technology (IIT) Indore, INDIA, under the supervision of Prof. Anirban Sengupta. IIT Indore holds the 396th rank in the QS World University ranking. In addition to this, IIT Indore has secured 14th rank in NIRF (National Institute ranking framework 2023) India.

My doctoral dissertation work focuses on developing robust and efficient solutions for hardware security while also creating secure and cost-effective hardware accelerators tailored for computationally intensive application frameworks using High-Level Synthesis (HLS). Throughout my Ph.D. journey, I've primarily concentrated on devising reliable design methodologies to ensure hardware security and trust. I've contributed to various esteemed peer-reviewed SCI Indexed journals including IEEE Transactions on Consumer Electronics, IEEE Transactions on Very Large-Scale Integration (VLSI) Systems, IEEE Transactions on Dependable and Secure Computing, IEEE Access, IEEE Consumer Electronics Magazine, IEEE IT Professional, IEEE Design and Test, and Elsevier Journal on Computers and Electrical Engineering, among others. Additionally, my work has been featured in reputed IEEE conferences and book chapters.

I also worked as a regular Post-Doc researcher (Aug 2023-June 2024) under Translational research fellowship scheme of IIT Indore, India. This fellowship was awarded to me in order to commercialize my PhD research work. As an outcome we developed a ‘Hardware Security CAD Software platform’ named "SOFTDEEP", available publicly for download/installation launched under "CAD for Assurance” global initiative by IEEE Council on Electronic Design Automation (CEDA) and IEEE Hardware Security and Trust Technical Committee (HSTTC).

SOFTDEEP: HLS based IP Protection Tool (for Secure Optimal Fault Tolerant Designs with Embedded Encrypted Protein Signature) Product publicly is available at the following websites.

https://cadforassurance.org/tools/ip-ic-protection/softdeep/

I joined the Indian Institute of Information Technology (IIIT) Bhopal, India, as an Assistant Professor in the Department of Computer Science and Engineering (CSE) on August 23, 2024. I am excited to contribute to the academic and research environment at IIIT Bhopal and aim for excellence in education, research, and innovation. My goal is to further strengthen the solid foundation that IIIT Bhopal has established in engineering and technology.

Currently, I am exploring new research areas with the aim of designing secure and efficient hardware accelerators tailored for applications in healthcare, machine learning (ML), multimedia, digital signal processing, and vital consumer electronics domains. Additionally, I am captivated by the potential of developing secure hardware accelerators for quantum computation and blockchain applications, along with those for Internet of Things (IoT) systems, while seamlessly integrating quantum security and blockchain-based security measures into different aspects of hardware security. I also possess a keen interest in designing secure and cost-effective hardware co-processors. Looking ahead, I intend to focus my efforts on exploring biometrics and machine learning-based solutions for hardware security, thereby further expanding my contributions in these fields.

Research Interests:

Hardware security,
Trustworthy Integrated Circuit (IC) design
High-level Synthesis
Hardware Architectural Optimization
Hardware Acceleration
Electronic Design Automation (EDA) for secure chips and systems
Biometric Constraints based Hardware Intellectual Property (IP) Watermarking
Secure RTL designs etc.

Latest Accepted Papers/News updates:

Our project, "Hardware-Assisted Systems for AMR Diagnostics," has been approved under the PAIR (Partnerships for Accelerated Innovation and Research) programme by the ANRF (Anusandhan National Research Foundation). It has received a grant of ~₹50Lakhs.
Leveraging Architectural Obfuscation and Encoded Palmprint-Hash for Securing Hardware IP Designs used in CE Systems, has been accepted for publication in IEEE Access, June 2026.
Joined as a Chapter Secretary, IEEE Consumer Technology Society (CTSoc) chapter, MP Section (Oct. 2024-present).
"Secure Implantable Cardiac Pacemaker for Medical Consumer Electronics", Nature - npj Biomedical Innovations, Accepted, Jan 2025.
"Secure Accelerated Computing: High-Level Synthesis Based Hardware Accelerator Design for CNN Applications, Proceedings of 10th IEEE International Symposium on Smart Electronic Systems (IEEE – iSES) , Accepted, Dec. 2024.
"SWIFT: Swarm Intelligence Driven ESL Synthesis for Functional Trojan Fortification", Proceedings of 10th IEEE International Symposium on Smart Electronic Systems (IEEE – iSES) , Accepted, Dec. 2024.
"Exploiting Retina Biometric Fused with Encoded Hash for Designing Watermarked Convolutional Hardware IP against Piracy", Springer Nature Computer Science (SNCS), Accepted, Aug. 2024.
"HLS Based Hardware Watermarking of Blur, Embossment and Sharpening Filters Using Fused Ocular Biometrics and Digital Signature" 37th IEEE International System-on-Chip Conference (IEEE- SOCC), 2024, Dresden, Germany.

Events:

Contributed as session chair in IEEE International Conference iCONECCT-2025, INDIA, during Dec. 26-28, 2025.
Contributed as session chair in IEEE IC-DECoN 2025, INDIA, during Dec. 12-13, 2025.
Contributed as Member TPC in IEEE- iSES, 2025, INDIA, during Dec. 13-17, 2025.
Attended IEEE- iSES, 2024, as session chair, held in New Delhi, INDIA, during Dec. 16-18, 2024.
Attended 37th International Conference on VLSI Design (VLSID-2024), for presenting the research work “HLS based Hardware Security and IP Protection,” SRF, Kolkata, INDIA, during Jan 6-10, 2024.
Attended 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT-2023), for presenting our research work "Fault Secured JPEG-Codec Hardware Accelerator with Piracy Detective Control using Secure Fingerprint Template" at ANTIPOLIS - Palais des Congrès d'Antibes in the city of Juan-Les-Pins, France, during oct. 03-05, 2023.
Attended and presented a paper in AsianHOST, 2023, held in Tianjin, China, during Dec. 13-15, 2023.
Attended and presented two papers in IEEE- iSES, 2023, held in Ahmedabad, INDIA, during Dec. 18-20, 2023.
Attended and presented two papers in IEEE- iSES, 2022, held in Warangal, INDIA, during Dec. 19-21, 2022.
Attended and presented two papers in IEEE- INDICON 2022, held in Kochi, INDIA, during Nov. 24-26, 2022.
Attended and presented a paper in IEEE- iSES, 2021, held in Jaipur, INDIA, during Dec. 20-22, 2021.
Attended ’1st Indian Workshop on Artificial Intelligence (iWAI) 2021’ held in IIT Indore, during March 19-25, 2021.