Designed an autonomous, self-improving agent that evolves cache‐replacement policies by closing the loop between LLM code generation, ChampSim feedback (rewarded by cache hit rate), and FunSearch-style evolutionary selection.
Implemented an end-to-end generative pipeline—retrieval/DAG-augmented prompting, code synthesis/parsing, automatic compilation, simulation, and policy archiving—that produces compilable, interpretable C/C++ policies ready for ChampSim evaluation.
Analyzed design levers (persona conditioning vs. none, prompt variants, trace complexity) and surface practical insights—e.g., stability/volatility trade-offs, simulation bottlenecks from complex generated logic, and risks of overfitting in dual feedback loops.
Analysis of Linear Convergence in Federated Learning: Overcoming Client Heterogeneity and Sparse Gradient Challenges
Wrote a review paper on major federated learning (FL) algorithms, including FedAvg, FedProx, FedNova, and FedLin, focusing on their convergence behaviors and how effectively they reach consensus in an FL setup.
Addressed the central challenges inherent in FL, such as objective and systems heterogeneity, along with the complexities of limited and unreliable communication.
Explored the trade-offs between speed and accuracy within these algorithms, providing valuable insights into their computational efficiency and precision in practical applications.
In this project, modeling and design of the artificial neural network, regression tree, multiple linear regression, and curve fitting model for load forecasting is carried out in the BUET academic and residential area. These approaches help to reduce the problems associated with the conventional method and have the advantage of learning directly from historical data. The forecasting models here have used data such as past load, and weather information like dew point and temperatures.
The actual data are taken from the BUET POWER PLANT. The data of load for the year 2005 is collected for a particular region and used to create an arbitrary dataset for 20 years. The main objective is to forecast the amount of electricity needed for better load distribution in the area.
Using different methods for forecasting gives the chance to compare their performances and choose the best out of them and that leads to creating an averaging model to take the best three of them and get a better result.
In this project, we have designed a system that will convert the texts written on an image to speech. To accomplish that task, we have utilized the functionalities of "Optical Character Recognition (OCR)" in Matlab.
Moreover, to extract the words or letters of an image, the Matlab image processing toolbox is used. After the extraction of words, the OCR function is used to recognize the extracted words. In the final phase, using the Matlab speech processing toolbox, we converted those words into speech. In a nutshell, if we nourish the project at an industrial level, this will prove a huge benefit for the handicapped and blind people.
In this project, our main goal was to reproduce the result of the paper "Variable Gain Control for Respiratory Systems. " In this paper, an innovative idea for controlling a mechanical ventilator is proposed. In fact, this control mechanism will be variable in nature, which means that the ventilator will adjust the pressure according to the needs of the patient. Keeping the gravity of the pandemic situation in mind, this literature is undoubtedly a significant addition to the control mechanisms of ventilators.
Traffic light plays an important role in controlling the traffics in urban area. It helps to reduce traffic jam and prevent accidents. Traffic light controller is designed for a four roads junction with eight lenses. It will generate a sequence of digital data to switch the color of the traffic light among red, green and yellow. We have used the idea of Finite State Machine (FSM) to define different states.
For this project we have used Quartus and Proteus in software part to implement the coding and synthesis the circuit. For the analysis part we have wave form analysis and circuit analysis using Proteus.
In this project, we have implemented a "Bangla Digital Clock" using an ARM cortex microprocessor. Specifically, STM32F 103R6 has been utilized in this implementation. Moreover, LED matrix display has been used to show the hour, minute, and second. Additionally, buttons have been integrated for adjustment purposes. For coding purposes, we have used "ARM KEIL" IDE. Finally, the circuit was built and simulated using "Proteus."
In this project, a 4-bit PC is designed according to the basic architecture of "Simple As Possible(SAP)-1." For accomplishing that task, "VerilogHDL" language has been used and "Quartus" software is utilized for simulation and writing of testbench code.
4 bit pc accomplishes all its instruction using 4 bit computing method.In computer architecture, 4-bit integers, memory addresses, or other data units are those that are 4 bits wide. Also, 4-bit CPU and ALU architectures are those that are based on registers, address buses, or data buses of that size. A group of four bits is also called a nibble and has 16 possible values. Its primary purpose is to develop a basic understanding of how a microprocessor works, interacts with memory and other parts of the system like input and output. The instruction set is very limited and is simple.