Partial Reconfiguration

What is Partial Reconfiguration?

The type of reconfigurable designs implemented in an FPGA in which a part of the design remain stable and the other half changes its architecture depending on the situation and need of the environment is called Partial Reconfiguration. In short, it is also known as PR.

Partial Reconfiguration or Dynamic Partial Reconfiguration consist of 2 parts:

Ø Static Region

Ø Dynamic Reconfigurable Region

The portion of the FPGA which remains stable during the entire operation of the design is called Static Region. The static region generally consists

of a controller usually a hardcore or softcore microprocessor which contains the time multiplexing and swapping logic. The other half which changes its architecture during runtime is called Reconfigurable Region. The reconfigurable region changes its architecture by loading bitstreams from memory depending on the situation.

Basic Structure of a Partially Reconfigurable FPGA design:

Partial Reconfiguration FPGA design

In the above design, the sky blue portion termed as Static Region is static region which contains the control logic for controlling the swapping and time multiplexing logic of the dynamic logic which consists of four reconfigurable regions. The entire system is conected with each other through a AXI bus based system. The partial bitstreams are loaded into the FPGA configuration memory via an

internal port called ICAP. The static bistream which consists of the initial partition is loaded via JTAG or PCIe in case of Xilinx FPGA.

Applications of Partial Reconfiguration:

•Software defined radio

•Digital Image and Signal Processing

•In PR, the hardware resources context switch in time domain.

•Radar in Air Traffic Management

•Encryption in communication modules

•Computer Networks

Architecture of a PR system developed at Idea Lab, University of Texas at Dallas


The above figure shows a typical AXI bus-Microblaze processor based PR design. The above system is capable of performing median and mean filtering applications in photographic images. The input image is stored in BRAM and output images is displayed via VGA monitor.

Floorplan of the PR Filter generated using PR_FP_TOOL viewed in Xilinx PlanAhead

Original Manual Floorplan Automated Floorplan by PR_FP_TOOL

Automated floorplan shown in the right is 80% area efficient compared to manual floorplan shown in the left. Timing wise the automated floorplan is around 400 times faster than the manual one.

My MS thesis on Partial Reconfiguration is attached below: