Experience

Title: EDA Software Engineer

Timeline: 10/21 - Present

Part of the core Placement and Routing team. My day to day job involves designing and modifying the placement part of the Lattice Radiant software used for FPGA programming. I am involved in solving customer bugs and optimizing performance. More specifically I redesigned the netlist partitioner of the placement tool using traditional analytical algorithms and GNNs.

Title: CAD Implementation Intern

Timeline: 5/20-8/20

Part of the synthesis methodology team. Developed a methodology by which a unit can be synthesized outside chiptree. Developed Python script which collects QOR results from synthesis run and sends to the user. Also, part of a project, which involved feature engineering and feature selection methodology for ML based clock gate latency prediction.

Title: Software Engineering Intern

Timeline: 5/18-8/18

Part of the FPGA Synthesis team for Synplify Pro and Protocompiler. Developed algorithm to map mathematical equations to DSP slice in FPGA using C++. Developed multi-input and wide input adder decomposition algorithm using Tree based structure. Obtained around 16% average improvement in timing for customized test circuits over existing algorithm.

Title: Software Development Engineer

Timeline: 6/16-8/17

Part of the Configuration Center of Excellence (COE). Involved in verification and charactererization (VnC) for config blocks of different Xilinx FPGA devices. Designed Partially Reconfigurable VnC test cases for Ultrascale+ devices like Zynq, Kintex and Virtex. The test cases checks the PR compatibility of resources like CLE, URAM, VCU, ADC/DAC etc. Modified the Vivado Software to make it PR compatible with blocks like VCU, ADC/DAC using C++.