About Me

I am a recent PhD graduate from University of Texas at Dallas (Graduated May, 2022). I am working as  EDA Software Engineer at Lattice Semiconductor, where my day to day job involve designing and developing placement tools for Lattice Radiant Software. My PhD was in ML based optimization of EDA tools, where I developed and optimized various RTL and HLS based EDA tools. The core of my research was predictive HLS tool designs, and its application in design space exploration and CNN accelerator development.

Previously, I have interned and did full time jobs in top EDA companies like Xilinx. Synopsys and Nvidia in various synthesis and placement and routing tool development roles mostly in C++.  I was advised by Dr. Dinesh Bhatia  during my MS and PhD. I also worked closely with Dr. Benjamin Carrion Schaefer during my PhD in various HLS and design space exploration research.

FPGA Floorplanning Benchmarks