V.K. Kakar, Munindra and P. K. Pal, “Gate-Induced Static and Dynamic Nonlinearity Characteristics of Bilayer Graphene Field-Effect Transistors (Bi-GFETs) ,” Micromachines, vol. 10, no. 09, pp. 1031, Sept. 2025, doi:. 10.3390/mi16091031 [Q2, SCI]
R. Tanwar, G. Singh, and P. K. Pal, “A Hybrid Transposed Attention Based Deep Learning Model for Wearable and Explainable Stress Recognition ,” Elsevier’ Computers and Electrical Engineering, vol. 119, Part B, pp. 109551, Aug. 2024, doi:. 10.1016/j.compeleceng.2024.109551 [Q1, SCI, IF: 4.0]
R. Tanwar, O. C. Phukan, G. Singh, P. K. Pal, and S. Tiwari, “Attention based hybrid deep learning model for wearable based stress recognition,” Elsevier’ Engineering Applications of Artificial Intelligence, vol. 127, Part B, pp. 107391, Jan. 2024, doi:. 10.1016/j.engappai.2023.107391. [Q1, SCI, IF: 8.0]
A. Bisht, Y. P. Pundir, and P. K. Pal, “Performance Analysis of Nanosheet Transistor with Drain/ Source Extension and High-k Spacer Optimizations for Analog Circuits,” Springer’s Analog Integrated Circuits and Signal Processing, vol. 116, pp. 37-45, Aug. 2023, doi:. 10.1007/s10470-023-02171-x. [SCI, IF: 1.4]
A. Bisht, Y. P. Pundir, and P. K. Pal, “Nanosheet Transistor with Inter-bridge Channels for Superior Delay Performance: A Comparative Study,” Springer’s Silicon, vol. 15, pp. 5175–5185, Mar. 2023, doi:. 10.1007/s12633-023-02432-4 [Q2, SCI, IF: 2.94]
Y. P. Pundir, A. Bisht, R. Saha, and P. K. Pal, “Effect of Process-Induced Variations on Analog Performance of Silicon-based Nanosheet Transistor,” Springer’s Silicon, vol. 15, pp. 4449–4455, Feb. 2023, doi: 10.1007/s12633-023-02365-y. [Q2, SCI, IF: 2.94]
Y. P. Pundir, A. Bisht, R. Saha, and P. K. Pal, “Effect of Temperature on performance of 5-nm node Silicon Nanosheet Transistors for Analog Applications,” Springer’s Silicon, vol. 14, no. 16, pp. 10581–10589, March 2022, doi: 10.1007/s12633-022-01800-w. [Q2, SCI, IF: 2.94]
R. Saha, Y. P. Pundir, and P. K. Pal, “Comparative Analysis of STT and SOT based MRAMs for Last Level Caches,” Elsevier’ Journal of Magnetism and Magnetic Materials, vol. 551, pp. 169161, Feb. 2022, doi: 10.1016/j.jmmm.2022.169161. [Q2, SCI, IF: 3.097]
Y. P. Pundir, A. Bisht, R. Saha, and P. K. Pal, “Air-spacers as Analog-performance booster for 5 nm-node N-channel nanosheet transistor,” IOP Semiconductor Science and Technology, vol. 36, no. 9, pp. 095037, Sept. 2021, doi:10.1088/1361-6641/ac16e6. [Q1, SCI, IF: 2.361]
R. Saha, Y. P. Pundir, and P. K. Pal, “Design of an area and energy-efficient last-level cache memory using STT-MRAM,” Elsevier’ Journal of Magnetism and Magnetic Materials, vol. 529, pp. 167882, Feb. 2021, doi: 10.1016/j.jmmm.2021.167882. [Q2, SCI, IF: 3.097]
Y. P. Pundir, R. Saha, and P. K. Pal, “Effect of gate length on performance of 5nm node N-Channel nano-sheet transistors for analog circuits,” IOP Semiconductor Science and Technology, vol. 36, no. 1, pp. 015010, Oct. 2020, doi:10.1088/1361-6641/abc51e. [Q1, SCI, IF: 2.361]
S. Verma, P. K. Pal, S. Mahavar and B. K. Kaushik, “Performance Enhancement of STT MRAM Using Asymmetric-k Sidewall-spacer NMOS,” IEEE Transactions on Electron Devices, vol.63, no. 7, pp.2771-2776, July 2016, doi:10.1109/TED.2016.2570602. [Q1, SCI, IF: 2.913]
P. K. Pal, B. K. Kaushik, and S. Dasgupta, “Asymmetric dual-spacer tri-gate FinFET device-circuit codesign and its variability analysis,” IEEE Transactions on Electron Devices, vol.62, no.4, pp.1105-1112, Apr. 2015, doi:10.1109/TED.2015.2400053. [Q1, SCI, IF: 2.913]
P. K. Pal, B. K. Kaushik, and S. Dasgupta, “Investigation of symmetric dual-k spacer trigate FinFETs from delay perspective,” IEEE Transactions on Electron Devices, vol.61, no.11, pp.3579-3585, Nov. 2014, doi:10.1109/TED.2014.2351616. [Q1, SCI, IF: 2.913]
P. K. Pal, B. K. Kaushik, and S. Dasgupta, “Design metrics improvement for SRAMs using symmetric dual-k spacer (SymD-k) FinFETs,” IEEE Transactions on Electron Devices, vol.61, no.4, pp.1123-1130, Apr. 2014, doi:10.1109/TED.2014.2304711. [Q1, SCI, IF: 2.913]
P. K. Pal, B. K. Kaushik, and S. Dasgupta, “High-performance and robust SRAM cell based on asymmetric dual-k spacer FinFETs,” IEEE Transactions on Electron Devices, vol.60, no.10, pp.3371-3377, Oct. 2013, doi:10.1109/TED.2013.2278201. [Q1, SCI, IF: 2.913]
S. Sharma, R. Chandel, P. K. Pal, and R. Rathore, “Performance analysis of CNTs as an application for future VLSI interconnects,” Jour. of Microelec. and Solid-State Electron., vol.1, no.3, pp.69-73, 2012, doi:10.5923/j.msse.20120204.04.