Conferences and Symposiums

R. Tanwar, G. Singh and P. K. Pal, "FuSeR: Fusion of wearables data for StrEss Recognition using explainable artificial intelligence models," in IEEE 14th International Conference on Computing, Communication and Networking Technologies  (ICCCNT 2023) at IIT - Delhi, Delhi India, 6-8 July 2023, pp. 1-6, doi: 10.1109/ICCCNT56998.2023.10307589.

A. Bhatt, M. K. Aghwariya, S. Pathak, P. K. Pal, A. Kumar, and T. Goel, “Model-Based Decomposition of Alakananda River Basin using SAR Data” in IEEE International Conference on Microwave Antenna and Communication (IMAC 23) at MNNIT Allahabad Prayagraj, India, 24-26 March 2023, pp. 1-6, doi: 10.1109/MAC58191.2023.10177102. 

V. K. Kakar and P. K. Pal, "Design and Investigation of Stacked Nanosheet Transistor Parameters for Analog Performance," in IEEE Proc. of International Conference on “Device Intelligence, Computing and Communication Technologies  (DICCT-2023) at Dehradun, India, 17-18 March 2023, pp. 95-99, doi: 10.1109/DICCT56244.2023.10110055. 

S. Pathak, M. K. Aghwariya, A. Bhatt, P. K. Pal and T. Goel, "Multi-Band Rectenna Integrated With Solar Cells for Microwave Energy Harvesting System," in Proc. IEEE Microwave, Antennas, and Propagation Conference (MAPCON), Bengaluru, India, 12-15 Dec. 2022, pp. 399-403, doi: 10.1109/MAPCON56011.2022.10046803.

Y. P. Pundir, A. Bisht, R. Saha, A. S. Bahuguna, K. Kumar and P. K. Pal, "Power Supply Variations and Analog Performance of 5-nm Node Silicon Nanosheet Transistor," in IEEE Proc. International Conference on Advances in Computing, Communication and Materials  (ICACCM-2022) at Tula's Institute, Dehradun, India, 10-11 Nov. 2022, pp. 1-5, doi: 10.1109/ICACCM56405.2022.10009092. 

Y. P. Pundir, R. Saha and P. K. Pal, "Mixed-mode circuit simulations with 5 nm Node Nanosheet Transistors using TCAD," in IEEE Proc. Intl. Conf. on Advances in Computing, Communication & Materials (ICACCM), Dehradun, India, Aug. 21-22, 2020, pp. 380-384, doi: 10.1109/ICACCM50413.2020.9212882.

R. Saha, Y. P. Pundir, S. Yadav and P. K. Pal, “Impact of Size, Latency of Cache-L1 and Workload Over System Performance” in IEEE Proc. Intl. Conf. on Advances in Computing, Communication & Materials (ICACCM), Dehradun, India, Aug. 21-22, 2020, pp. 390-393, doi: 10.1109/ICACCM50413.2020.9213015. 

R. Saha, Y. P. Pundir, and P. K. Pal, “An energy-efficient and moderate speed non-volatile memory for IoT application” in Proc. online Intl. Conf. on Communication, Computing and Signal Processing -2020 (CCSP-2020), Jalandhar, Punjab, India, July 23-24, 2020.

P. Kumar, S. Yadav, and P. K. Pal, “Analysis of Nano-sheet Field Effect Transistor (NSFET) for device and circuit perspective” in IEEE Proc. 2nd Intl. Conf. Women Institute of Technology Conference on Electrical and Computer Engineering-2019 (WITCON ECE), Dehradun, India, Nov. 22-23, 2019, pp. 183-186, doi: 10.1109/WITCONECE48374.2019.9092925.

R. Saha, R. K Singh, R. Kumar, G. Singh, T. Goel, and P. K. Pal, “Classification of Human Heart Signals by Novel Feature Extraction Techniques for Rescue Application” in IEEE Proc. 5th Intl. Conf. on Image Information Processing (ICIIP-2019), Solan, India, Nov. 15-17, 2019, pp. 156-160, doi: 10.1109/ICIIP47207.2019.8985727.         

D. S. Kushwaha, A. K. Rai, S. Agrawal, P. K. Pal, and H. K. Singhal, “A Narrow Band Cascode Source Degeneration Low Noise Amplifier with π-Input Matching at 5 GHz Frequency” in IEEE Proc. 2nd  Intl. Conf. on Innovations in Electronics, Signal Processing and Communication (IESC), Shillong, India, Mar. 1-2, 2019, pp. 301-304, doi: 10.1109/IESPC.2019.8902452.

R. K. Singh, R. Saha, P. K. Pal, and G. Singh, “Novel Feature Extraction Algorithm using DWT and Temporal Statistical Techniques for Word Dependent Speaker's Recognition” in IEEE Proc. 4th Intl. Conf. on Research in Computational Intelligence and Communication Networks (ICRCICN), Kolkata, Nov. 22-23, 2018, pp. 130-134, doi: 10.1109/ICRCICN.2018.8718681.  

Manoj Kumar, P. K. Pal, and S. Yadav, “SET Detection and Radiation Hardened Pipelined 8-bit ADC Using 180 nm Technology” in IEEE Proc. 2nd  Intl. Conf. on Trends in Electronics and Informatics (ICOEI-2018), Tirunelveli, Tamilnadu, May 11-12, 2018, pp. 1240-1245, doi: 10.1109/ICOEI.2018.8553700.

Lokanshu Kumar, P. K. Pal, and H. K. Singhal, “An Advance Architecture of Magnetic Random Access Memory” in IEEE Proc. 2nd  Intl. Conf. on Trends in Electronics and Informatics (ICOEI-2018), Tirunelveli, Tamilnadu, May 11-12, 2018, pp. 1235-1239, doi: 10.1109/ICOEI.2018.8553940.

P. K. Pal, B. K. Kaushik, and S. Dasgupta, “A detailed capacitive analysis of symmetric and asymmetric dual-k FinFETs for improved circuit delay metrics,” in Proc. IEEE Conf. on Emerging Devices and Smart Systems (ICEDSS-2016), Mallasamudram, Tamilnadu, March 4-5, 2016, pp. 13-18, doi: 10.1109/ICEDSS.2016.7587790.

P. K. Pal, D. Nehra, B. K. Kaushik, and S. Dasgupta, “Enhanced device-circuit co-design performance using lightly doped channel junctionless accumulation-mode (LDC-JAM) FinFET,” in IEEE Proc. 12th Intl. Conf. on Electrical Engineering/Electronics, Computer, Telecommunications and Information Technology (ECTI-CON-2015), Hua-hin, Thailand, June 24-27, 2015, pp. 1-5, doi: 10.1109/ECTICon.2015.7206988. 

P. K. Pal, S. Verma, B. K. Kaushik, and S. Dasgupta, “Statistical variability and sensitivity analysis of dual-k spacer FinFET device-circuit co-design,” in IEEE Proc. of 11th Intl. Conf. on Electron Devices and Solid-State Circuits (EDSSC 2015), Singapore, June 1-4, 2015, pp. 190-193, doi: 10.1109/EDSSC.2015.7285082.

S. Mahawar, S. Verma, P. K. Pal, and B. K. Kaushik, “Highly reliable STT-MRAM using fully depleted body and buried 4H-SiC NMOS,” in IEEE Proc. of 11th Intl. Conf. on Electron Devices and Solid-State Circuits (EDSSC 2015), Singapore, June 1-4, 2015, pp. 701-704, doi: 10.1109/EDSSC.2015.7285214.

P. K. Pal, B. K. Kaushik, B. Anand, and S. Dasgupta, “A comparative analysis of symmetric and asymmetric dual-k spacer FinFETs from device and circuit perspectives,” in IEEE Proc. of 16th Intl. Symp. on Quality Electronic Design (ISQED’15), Santa Clara, CA, USA, March 2-4, 2015, pp. 594-598, doi: 10.1109/ISQED.2015.7085494.

D. Nehra, P. K. Pal, B. K. Kaushik, and S. Dasgupta, “High permittivity spacer effects on junctionless FinFET based circuit/SRAM applications,” in IEEE Proc. of 18th of Int. Symp. on VLSI Design and Test (VDAT-2014), Coimbatore, India, July 15-18, 2014, pp.1-6, doi: 10.1109/ISVDAT.2014.6881054.

P. K. Pal, B. K. Kaushik, and S. Dasgupta, “Low-power and robust 6T SRAM cell using symmetric dual-k spacer FinFETs,” in IEEE Proc. of 29th Int. Conf. on Microelectronics (MIEL-2014), Belgrade, Serbia, May 12-15, 2014, pp. 103-106, doi: 10.1109/MIEL.2014.6842096.

P. K. Pal, P. Singh, B. K. Kaushik, B. Anand, and S. Dasgupta, “Performance analysis of dual-k spacer at source side for underlap FinFETs,” in IEEE Proc. of Annual India Conf. (INDICON-2012), Trivandrum, Kerala, Dec. 7-9, 2012, pp. 915-919, doi: 10.1109/INDCON.2012.6420747.

P. K. Pal, R.S. Rathore, A.K. Rana, and G. Saini, “New low-power techniques: Leakage feedback with stack and sleep stack with keeper,” in IEEE Proc. of Int. Conf. on Computer and Communication Technology (ICCCT-2010), Allahabad, UP, Sept. 17-19, 2010, pp.296-301, doi: 10.1109/ICCCT.2010.5640514.

G. Saini, A.K. Rana, P. K. Pal, and S. Jadav, “Leakage behavior of underlap FinFET structure: A simulation study,” in Proc. IEEE Int. Conf. on Computer and Communication Technology (ICCCT-2010), Allahabad, UP, Sept. 17-19, 2010, pp.302-305, doi: 10.1109/ICCCT.2010.5640528.

R. S. Rathore, P. K. Pal, and A. Sharma, “A 1-V 8-Bit 100M-samples/s fully-differential low power sample-and-hold amplifier in 0.05-µm CMOS,” in Proc. of 1st Int. Conf. on Adaptive Computing in Various Engineering Applications (ICACTEA-2011), Jaipur, Rajasthan, Feb. 24-26, 2011, pp. 1-4.

P. K. Pal, B.K. Kaushik, and S. Dasgupta, “Performance improvement for underlap FinFETs using dual-k spacer,” Nat. Seminar on Progress in Electronics and Applied Sc., Haridwar, Uttarakhand, Oct’2012.

P. K. Pal, R.S. Rathore, and A.K. Rana, “Gate engineering effect on bulk, FDSOI and DG MOSFET devices,” Nat. Seminar on Inno. And Application in Engg. and Applied Sc., Haridwar, UK, Nov’2011.

R. S. Rathore, P. K. Pal, and A. Sharma, “A New Emerging Technology of ballistic deflection transistor in nano-scale electronics”, Nat. Conference on Recent Trends in Electronics, Meerut, UP, April’2011.

R. S. Rathore, P. K. Pal, and A. Sharma, “Comparison analysis and optimization of current mirror”, National Conference on Emerging Technologies and Applications (ETA-2010), Jaipur, Raj., Feb’2010.