Books/Book Chapters
Spacer Engineered FinFET Architectures
High-Performance Digital Circuit Applications
By Brajesh Kumar Kaushik, Sudeb Dasgupta, Pankaj Kumar Pal
Edition: 1st Edition
First Published: 2017
eBook Published: 16 June 2017
Pub. Location: Boca Raton
Imprint: CRC Press
DOI: https://doi.org/10.1201/9781315191089
Pages: 154
eBook: ISBN9781315191089
Subjects: Engineering & Technology
Book Chapters:
Bisht, A., Pundir, Y.P., Pal, P.K. (2022). Electro-Thermal Analysis of Vertically Stacked Gate All Around Nano-sheet Transistor. In: Shah, A.P., Dasgupta, S., Darji, A., Tudu, J. (eds) VLSI Design and Test. VDAT 2022. Communications in Computer and Information Science, vol 1687. Springer, Cham. https://doi.org/10.1007/978-3-031-21514-8_12.
Pal, P.K., Kaushik, B.K., Dasgupta, S. (2013). Optimization of Underlap FinFETs and Its SRAM Performance Projections Using High-k Spacers. In: Gaur, M.S., Zwolinski, M., Laxmi, V., Boolchandani, D., Sing, V., Sing, A.D. (eds) VLSI Design and Test. Communications in Computer and Information Science, vol 382. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-42024-5_32