Lab 1: Seven segment decoder

Part 1: LED Decoder

This project was a simple implementation of a Vivado VHDL project on the XILINX Digilent A7-100T FPGA board

One VHDL source file and one .xdc constraint file compose the core of this project - in my case, both were named "leddec.FILETYPE"

Once synthesized, implemented and programmed, the program transformed the four rightmost switches into a 4-bit binary switch to determine the hexidecimal state (0-F) of the four rightmost LED panels. Simultaneously, switches 7 & 8 became a 2-bit switch to determine the position of the LED on the lefthand side

View the LED Decoder Vivado Project on GitHub

Part 2: hexidecimal counter

This hexidecimal counter was built as an extention to the LED decoder project, continuing to work through Vivado VHDL on the XILINX Digilent A7-100T FPGA board

In addition to the VHDL source file of the LED decoder (leddec.vhd), the hexidecimal counter adds two additional source files to the Vivado project (counter.vhd & hexcounter.vhd). The LED decoder's constraint file has been replaced with a new version, hexcount.xdc.

Once synthesized, implemented and programmed, the FPGA will use its four rightmost LED indicators to iterate through 4 bits hexidecimally (0-F). The switches no longer affect the LED functionality

View the Hexidecimal Counter Project on GitHub

Page updated

Google Sites

Report abuse