The global coronavirus pandemic is/was more than anyone could have anticipated, and has presented novel challenges to collegiate education across the country and the planet. In the context of this Digital System Design, course the foremost of these challenges is access to hardware, necessary for the execution of many labs but wholly inaccessible to both teachers and students barred from accessing campus in a national quarantine. In a situation such as this, we rely on innovation to find new solutions to these problems. As such, I've used the resources I have available to replace the PMOD ADC & Potentiometer necessary to move the paddle in Lab 6 - Pong Game. With the contribution I detail here, DSD students next semester who may still be learning remotely can complete Lab 6 without specialized hardware.

The first version of this project aimed to emulate the functionality of the PMOD analog-to-digital converter with an external microprocessor, such as the Arduino or Raspberry Pi I have lying around. Such an implementation would have required the following materials:

1. One Xilinx Diligent Nexys-A7100T FPGA board
2. A Vivado installation with a working copy of my Lab 6 code, accessible here
3. 1 Arduino (Mega2560 used here, but any version should suffice)
4. Likewise, an installation of the Arduino IDE for installation and testing of the code
5. A digital-to-analog converter, or sufficient resistors to build an R-2R ladder as I've done
6. The VGA monitor required for Lab 6

After a few iterations of trying to emulate a digital signal with user input from the RPi/Arduino, I faced two immutable facts:

• Plugging customized circuitry into the JA ports poses an increased risk to the Nexys A7-100T board
• Not everyone in next year's class will have access to RPis/Arduinos at home; I am violating my own thesis

Therefore, the third design iteration aimed to eliminate all unnecessary hardware and write VHDL code on the FPGA itself to control the paddle's motion on the VGA screen. Since its motion is only on one axis, there is only a need for two inputs to control left/right motion - therefore, the BTNL & BTNR buttons should provide all the user input necessary.

Lab 6 is supposed to be a game of pong; the user tries to bounce a ball around by controlling the position of a one-dimensional paddle with an analog signal, generated by a potentiometer. This analog signal is sampled by the PMOD ADC device, and an SPI-adjacent digital signal is presented to the JA port on the board. This signal is directly sampled by the adc_if.vhd source, using headers defined in the pong.xdc constraint file to interface directly with the hardware. The architecture of this 'adc_if' entity is fairly concise, and is shown to the left (top). The component has six ports; four inputs from the JA, including two data ports (SDATA1,SDATA2), a clock signal SCK and a chip select signal CS, and two outputs data_1 & data_2, each containing the digital data from their respective inputs. The architecture only defines two processes; adpr uses the CS signal and SCK clock to collect 11 bits of data on a falling clock edge, then shifts the data to the output ports on the rising edge.

This signal is then piped to the main behavioral file, pong.vhd in a component definition. I've included the relevant snippets to the left - note the six ports on the component definition, of which we only truly care about data_1 and data_2 with regard to the paddle movement. Farther down the file, the entity is mapped more definitevly, where we discover that the data_1 signal is discarded altogether and the data_2 signal is redirected to another standard logic vector, 'adout'. This signal is only used once in the entire program, shown to the left as the final line where it is used to set the state of an 11-bit 'batpos' signal. This seemed to be the easiest point in the program to manipulate the signal and reroute control of the bat motion.