Research

Neural Interface IC for Future Brain-Computer Interfaces

Fig. 1 Simplified diagram of brain-computer interfaces

Brain-computer interfaces (BCIs) have the potential to revolutionize therapy for neurological diseases because they target the nervous system with high spatiotemporal resolution as opposed to pharmacological, surgical, or gene therapies. By recording activation patterns of nervous systems, we can decode the patient's intention into neural code for controlling devices such as computer, smart phone, etc. Reversely, by encoding the neural code, and stimulating nervous systems, a patient can recover natural functionalities from various neurological disorders. As an example, the recent BCI clinical trial by Neuralink is below.

Link: First Person With Elon Musk's Neuralink Chip

Next-generation Brain-Computer Interface Chip

Fig. 2 Simplified diagram of future smart brain-computer interface systems and its key features

Next-generation BCIs for clinical applications will benefit from an implantable neural interface integrated circuit (IC) with a dense, high channel count array that can be directly matched to a micro-electrode array (MEA) at the pitch of neurons (≈ 30 µm) to capture spatiotemporal patterns of neural activity at single-cell resolution. Future BCIs must support simultaneous recording from tens of thousands of neurons within a fully implanted device's form factor and power budget. We aim to develop a high-channel count (>10k), high-density (channel pitch < 30µm) implantable neural interface IC for future smart BCI systems (Fig. 2). The key features of neural interface IC for future BCI systems include 1) Large # of channels, 2) Single-cell resolution, 3) Reconfigurability, 4) Neural code reproduction, and 5) Embedded on-chip machine learning (ML) processor.

High-Performance Data Converter for Various Applications

Fig. 3 Examples of data converter applications

Data converters, especially analog-to-digital converters (ADCs) are everywhere in all kinds of mixed-signal integrated circuits (ICs) and systems. For example, most sensor interface ICs include analog-to-digital conversion whose inputs are analog signals from different sensing objects (e.g., audio, image, biomedical, etc.). Wireless communication system requires highly linear wideband ADCs in a receiver chain. High-fidelity audio applications require high-resolution ADCs and digital-to-analog converters (DACs). Wireline communication systems (e.g., hybrid fiber-coaxial networks) require wideband ADCs. Therefore, in-depth knowledge about the design methodology of energy-efficient ADCs in all classes such as successive-approximation register (SAR), pipeline, delta-sigma, and others is important to develop the most efficient system for specific applications. To help along this path, the review article below discusses the design techniques that focus on optimizing ADC energy efficiency.

Link: Design Techniques for Energy-Efficient Analog-to-Digital Converters

1) High-performance ADC for Future Wireless Communication Systems

Fig. 4 Wireless receiver with standalone low-noise (LN) ADC for future wireless solutions

In recent years, the rapid development of multi-standard wireless communication systems demands high-performance ADC. In this research, the objective is to develop a wideband and high-resolution (i.e., low-noise (LN)) continuous-time (CT) delta-sigma ADC to deliver the next-generation wireless communication system baseband receivers with direct conversion to achieve energy-efficient wideband and high-resolution signaling to maximize system energy efficiency. As a result, future wireless communication systems for cost- and energy-efficient 5G or 6G solutions will be delivered to support a maximum data rate of 20 gigabits per second (Gbps) range for 5G, and up to 1,000 Gbps range for 6G protocol.

2) Smart Sensor Interfaces with Embedded Machine Learning

Fig. 5 Smart sensor interfaces utilizing signal conditioning and feature extraction and embedded machine learning

Sensor interfaces are essential for various sensing applications such as biomedical, voice recording, imager, etc. In this research, the objective is to develop smart sensor interfaces which include innovative A/D and D/A interfaces by utilizing signal conditioning and feature extraction at the front-end, and embedded low-power machine learning (ML) processors at the computational backend for on-chip computing in various sensing applications. Based on this idea, application-specific high-performance smart sensors will be developed by optimizing system performance while focusing on the design priority of the A/D interface depending on the sensing objects.