Publication

S. Chon, J. Yoon, M.-H. Jang, Y. Lim, and Y. Chae, "A 111-µW 100.8dB DR Audio Continuous-Time Delta-Sigma Modulator using Positive Feedback Amplifier," in IEEE European Solid-State Electronics Research Conference (ESSERC), 2025, Accepted.

W. Lee, H. Han, Y. Kwon, S. Yoon, J. Yoon, S. Lee, M. Jang, Y. Chae, ”A 500-kS/s Continuous-Time Linear-Exponential Incremental ADC Achieving 90.1-dB DR and 103.1-dB SFDR,” in IEEE Transaction on Circuits and System-I (TCAS-I), ISSN: 1558-0806, Accepted

J. Yoon, M. Jang, C. Lee, Y. Lim, Y. Chae, ”An Intrinsically Linear Multi‑Rate Continuous‑Time Zoom ADC Achieving 97.4‑dB DR and 105.7‑dB SFDR in 50‑kHz Signal Bandwidth,” in IEEE Journal of Solid‑State Circuits (JSSC), vol. 60, no. 2, pp. 432 - 442, ISSN: 0018‑9200, Feb. 2025 [link]

R. Doshi, M. Giordano, J. Olah, Z. Cao, M. Jang, L. R. Upton, A. Ramkaj, B. Murmann, ”Medusa: A 0.83/4.6 μJ/Frame 86/91.6% CIFAR‑10 tinyML Processor with Pipelined Pixel Streaming of Bottleneck Layers in 28nm CMOS,” in IEEE Symposium on VLSI Circuits, ISSN: 2158‑9682, June 2023 [link]

M. Jang, M. Hays, W. H. Yu, C. Lee, P. Caragiulo, A. Ramkaj, P. Wang, N. Vitale, P. Tandon, P. Yan, P. I. Mak, Y. Chae, E.J. Chichilnisky, B. Murmann, D.G. Muratore ”A 1024‑Channel 268nW/pixel 36×36μm2/channel Data‑Compressive Neural Recording IC for High‑Bandwidth Brain‑Computer Interfaces,” in IEEE Journal of Solid‑State Circuits (JSSC), vol. 59, no. 4, pp. 1123 ‑ 1136, ISSN: 0018‑9200, Apr. 2024, Invited paper [link]

M. Jang, X. Tang, Y. Lim, J. Kauffman, N. Sun, M. Ortmanns, Y. Chae ”Design Techniques for Energy‑Efficient Analog-to-Digital Converters,” in IEEE Open Journal of Solid‑State Circuits Society (OJSSCS), vol. 3, no. 9, pp. 145 ‑ 161, ISSN: 2644‑1349, Sept. 2023, Invited paper [link]

M. Jang, W. H. Yu, C. Lee, M. Hays, P. Wang, N. Vitale, P. Tandon, P. Yan, P. I. Mak, Y. Chae, E.J. Chichilnisky, B. Murmann, D.G. Muratore ”A 1024‑Channel 268nW/pixel 36×36μm2/ch Data‑Compressive Neural Recording IC for High‑Bandwidth  Brain‑Computer Interfaces,” in IEEE Symposium on VLSI Circuits, pp. 1 ‑ 2 (C1‑3), ISSN: 2158‑9682, June 2023 [link]

J. Yoon, M. Jang, C. Lee, Y. Lim, Y. Chae, ”A 243μW 97.4dB‑DR 50kHz‑BW Multi‑Rate CT Zoom ADC with Inherent DAC Mismatch Tolerance,” in IEEE Custom Integrated Circuits Conference (CICC), pp. 1 ‑ 6, ISSN: 2152‑3630, Apr. 2023 [link]

M. Jang, C. Lee, Y. Chae, ”A 134‑μW 99.4‑dB SNDR Audio Continuous‑Time Delta‑Sigma Modulator With Chopped Negative‑R and Tri‑Level FIR‑DAC,” in IEEE Journal of Solid‑State Circuits (JSSC), vol. 56, no. 6, pp. 1761 ‑ 1771, ISSN: 0018‑9200, June 2021 [link]

Y. Chae, M. Jang, C. Lee, S. Lee, S. Song, ”A Negative R‑Assisted Amplifier on the Virtual Ground and Its Applications,” in IEEE Custom Integrated Circuits Conference (CICC), pp. 1 ‑ 6, ISSN: 2152‑3630, Apr. 2021 Invited paper [link]

C. Lee, T. Jeon, M. Jang, S. Park, J. Kim, J. Lim, J. Ahn, Y. Huh, Y. Chae, ”A 6.5‑μW 10‑kHz BW 80.4‑dB SNDR Gm‑C Based CT Delta‑Sigma Modulator With a Feedback Assisted Gm Linearization for Artifact‑Tolerant Neural Recording,” in IEEE Journal of Solid‑State Circuits (JSSC), vol. 55, no. 11, pp. 2889 ‑ 2901, ISSN: 0018‑9200, Nov. 2020 [link]

M. Jang, C. Lee, Y. Chae, ”A 134‑μW 24kHz‑BW 103.5dB‑DR CT Delta‑Sigma Modulator With Chopped Negative‑R and Tri‑Level FIR DAC,” in IEEE International Solid‑State Circuits Conference (ISSCC), pp. 156 ‑ 158, ISSN: 2376‑8606, Feb. 2020 [link]

C. Lee, T. Jeon, M. Jang, S. Park, Y. Huh, Y. Chae, ”A 6.5‑μW 10‑kHz BW 80.4‑dB SNDR Continuous‑Time Delta‑Sigma Modulator With Gm‑Input and 300mVpp Linear Input Range for Closed‑Loop Neural Recording,” in IEEE International Solid-State Circuits Conference (ISSCC), pp. 410 ‑ 412, ISSN: 2376‑8606, Feb. 2020 [link]

Y. Kim, S. Park, S. Song, S. Lee, M. Jang, C. Lee, Y. Chae, ”A 41μW 16MS/s 99.2dB‑SFDR Capacitively Degenerated Dynamic  Amplifier with Nonlinear‑Slope‑Factor Compensation,” in IEEE International Solid‑State Circuits Conference (ISSCC), pp. 358 ‑ 360, ISSN: 2376‑8606, Feb. 2020 [link]

S. Song, J. Na, M. Jang, H. Lee, H. Lee, Y. Lim, H. Choi, Y. Chae, ”A CMOS VEGF Sensor for Cancer Diagnosis Using a Peptide Aptamer‑Based Functionalized Microneedle,” in IEEE Transactions on Biomedical Circuits and Systems (TBCAS), vol. 13, no. 6, pp. 1288 ‑ 1299, ISSN: 1932‑4545, Dec. 2019 [link]

S. Song, C. Lee, M. Jang, Y. Chae, ”A 185 μW ‑105.1 dB THD 88.6 dB SNDR Negative‑R Stabilized Audio Preamplifier,” in IEEE European Solid‑State Circuits Conference (ESSCIRC), pp. 261 ‑ 264, ISSN: 2643‑1319, Sept. 2019 [link]

S. Song, J. Na, M. Jang, H. Lee, H. Lee, Y. Lim, H. Choi, Y. Chae, ”A Capacitive Biosensor for Cancer Diagnosis Using a Functionalized Microneedle and a 13.7b‑Resolution Capacitance‑to‑Digital Converter from 1 to 100nF,” in IEEE International Solid‑State Circuits Conference (ISSCC), pp. 194 ‑ 196, ISSN: 2376‑8606, Feb. 2019 [link]

M. Jang, C. Lee, Y. Chae, ”Analysis and Design of Low‑Power Continuous‑Time Delta‑Sigma Modulator Using Negative‑R Assisted Integrator,” in IEEE Journal of Solid‑State Circuits (JSSC), vol. 54, no. 1, pp. 277 ‑ 287, ISSN: 0018‑9200, Jan. 2019 [link]

C.  Lee, M.  Jang, Y.  Chae, ”A 1.2V 68μW 98.2dB‑DR Audio Continuous‑Time Delta‑Sigma Modulator,” in IEEE Symposium on VLSI Circuits, pp.  199 ‑ 200, ISSN:  2158‑5601, June 2018 [link]

M. Jang, C. Lee, Y. Chae, ”A 55μW 93.1dB‑DR 20kHz‑BW single‑bit CT Delta‑Sigma Modulator with negative R‑assisted integrator achieving 178.7dB FoM in 65nm CMOS,” in IEEE Symposium on VLSI Circuits, pp. 40 ‑ 41, ISSN: 2158‑5601, June 2017 [link]