[8] Mixed‑signal Processing for High‑performance A/D Interfaces
Department of Electrical and Electronic Engineering, The Chinese University of Hong Kong (CUHK), Hong Kong, June 26, 2024.
[7] Mixed‑signal Processing for High‑performance A/D Interfaces
Department of Electrical and Computer Engineering, National University of Singapore (NUS), Singapore, Jan. 10, 2024.
[6] Neural Interface IC for Future Single‑cell Resolution Brain‑Machine Interfaces
Samsung Advanced Institute of Technology (SAIT), 130, Samsung‑ro, Suwon, Korea, July 11, 2023.
[5] Neural Interface IC for Future Single‑cell Resolution Brain‑Machine Interfaces
Department of Electronic and Electrical Engineering, Ewha Womans University, Seoul, South Korea, June 19, 2023.
[4] Neural Interface IC for Future Single‑cell Resolution Brain‑Machine Interfaces
Department of Electronic Engineering, Ulsan National Institute of Science and Technology (UNIST), Ulsan, South Korea, June 8, 2023.
[3] Neural Interface IC for Future Single‑cell Resolution Brain‑Machine Interfaces
Department of Electrical and Electronic Engineering, Yonsei University, Seoul, South Korea, June 1, 2023.
[2] A 1024‑Channel 268 nW/pixel 36×36μm2/ch Data‑Compressive Neural Recording IC for High‑Bandwidth Brain‑Computer Interfaces
Department of Neurosurgery, Stanford University, CA, USA, Feb. 10, 2023
[1] Continuous‑Time Delta‑Sigma ADCs: Past, Present, and Trends
Department of Electronic Engineering, Sogang University, Seoul, South Korea, Feb. 17, 2022.