As semiconductor devices become smaller, the interconnects connecting them must also shrink. At nanoscale dimensions, increased scattering and the space occupied by barrier and liner layers make it difficult for conventional metals to maintain low resistance. Interconnect resistance therefore becomes an increasingly important constraint on circuit speed and energy efficiency.
Topological semimetals offer alternative conductor concepts through their electronic structures and surface contributions to transport. Understanding how these contributions evolve with dimensions, disorder and interfaces is essential for assessing their potential as scaled contacts and interconnects.
Our research investigates size-dependent electrical transport and interface effects in emerging conductor materials, with an emphasis on topological semimetals. We study how material structure, surfaces and contact interfaces influence resistance as dimensions are reduced. By connecting materials engineering with electrical characterization and device integration, we aim to identify conductor structures and processing strategies suitable for future semiconductor contacts and interconnects.
Future interconnect development will increasingly span on-chip BEOL wiring and advanced packaging, requiring coordinated advances in conductors, interfaces, and integration processes. Thin-film processing, nanoscale transport analysis, and materials characterization provide a shared foundation for addressing resistance, reliability, and manufacturability across these scales.
Joon-Seok Kim, Joonyun Kim, Daejin Yang, Jaewoo Shim, Luhing Hu, Jeehwan Kim#, Sangwon Kim#,
"Addressing interconnect challenges for enhanced computing performance" Science, 386, 6727 (2024) Â