Dr. Bablu Mukherjee

Senior Engineer – NAND Design Rule & Design Enablement

Hyderabad, India | bablu.iitm@gmail.com | LinkedIn: linkedin.com/in/phybm | ORCID: 0000-0002-5625-5948

PROFESSIONAL SUMMARY

Accomplished semiconductor engineer with 10+ years leading 3D NAND design-rule and enablement programs across industry R&D. Deliver end-to-end PDK rule definition, DRC deck/runsets, and signoff readiness (DRC/LVS/ERC) for advanced 176-200+ layer architectures. Drive DTCO by aligning device physics, process integration, lithography/OPC, reticle, yield, and design execution. Reduced DRC violations 30-40% through layout analytics and hotspot debugging. Author of 26+ publications (1,382 citations, h-index: 17), 4 US patents, and recipient of Ramanujan, JSPS, and DAAD fellowships.

CORE COMPETENCIES

Design Enablement & PDK

• Clean-sheet NAND rules (176-200+ layers)

• DRC deck/runset development

• Signoff methodology (DRC/LVS/ERC)

• Waiver governance & tapeout readiness

DTCO & Manufacturability

• PI/Litho-OPC/Reticle/Yield alignment

• Layout-driven risk closure & DFM

• Rule scalability for advanced nodes

• Cross-functional DTCO signoff

Verification & Debug

• Calibre, KLayout, Mentor Graphics DRV/RVE

• Hotspot analysis & root-cause debugging

• Layout analytics & violation trending

Process & Device Technology

• PEALD/PEALE, area-selective processes

• 3D NAND device physics & reliability

• TCAD simulation, DoE (JMP), Python

PROFESSIONAL EXPERIENCE

Micron Technology, Inc. | Hyderabad, India | August 2022 – Present

Senior Engineer, NAND Design Rule (Advanced NAND Technology Team)

•       Own NAND PDK/DRC for 4 nodes: Translate PI requirements into clean-sheet rules and Calibre runsets; qualify decks and release tapeout-ready collateral for 176-200+ layer 3D NAND architectures.

•       Reduce DRC violations 30-40%: Build layout-hotspot analytics and debug Calibre checks; drive rule clarifications and designer feedback to accelerate signoff convergence.

•       Lead PI-facing DTCO signoff: Run cross-functional reviews (PI/Litho-OPC/Reticle/Yield/Design) to close manufacturability risks, define guard-banded rules, and prevent late-cycle churn.

•       Deliver >95% on-time milestones: Execute PDK release-to-tapeout readiness with rapid DRC debug turnaround to keep PI and design schedules on track.

•       Standardize waiver governance: Create criteria and review workflows with PI to improve consistency, reduce rework, and enable faster tapeout decisions.

•       Technical liaison: Serve as SRC liaison facilitating industry-academia collaboration and technology roadmap alignment (2021-Present).

ASM International N.V. | Nagoya, Japan | September 2020 – August 2022

Senior Process R&D Engineer (Corporate R&D) | Designated Assistant Professor, Nagoya University (Joint)

•       Develop PEALD/PEALE processes for advanced logic/memory to improve selectivity/uniformity and enable area-selective integration in single-reactor flow.

•       Optimize film quality using DoE (JMP) and in-situ diagnostics (ellipsometry/FTIR/OES) to reduce defectivity and variation.

•       Resolve gap-fill module issues for 3D NAND structures; author 4 US patents and support customer demos and technology transfer.

•       Lead academia-industry collaboration bridging plasma science and semiconductor manufacturing to accelerate technology transfer.

National Institute for Materials Science (NIMS) | Tsukuba, Japan | November 2017 – September 2020

Postdoctoral Fellow (JSPS Fellowship / MANA Fellowship)

•       Lead end-to-end nanoelectronics/NVM R&D from device architecture through cleanroom fabrication (EBL/photolithography) and electrical characterization.

•       Develop floating-gate NVM using 2D TMD heterostructures (ReS₂/h-BN/graphene), including multilevel optical-driven flash with high retention.

•       Publish 8 high-impact articles in Advanced Functional Materials, Advanced Electronic Materials, ACS Photonics; receive Excellent Poster Award (2019).

Indian Institute of Technology (IIT) Bombay | Mumbai, India | September 2015 – April 2017

Institute Postdoctoral Fellow, Optoelectronics & 2D Materials

•       Integrate plasmonics with ReS₂ to demonstrate high-responsivity phototransistors through enhanced light confinement.

•       Design and fabricate suspended devices to reduce substrate degradation and improve electrical/optical performance.

The George Washington University | Washington, D.C., USA | March 2014 – August 2015

Postdoctoral Research Scientist, Optoelectronics & 2D Materials

•       Design metamaterial-MoS₂ hybrids demonstrating broadband absorption enhancement in ultra-thin semiconductors.

•       Characterize complex electrical permittivity of monolayer MoS₂ (157 citations) in Optical Materials Express.

EDUCATION

Ph.D., Engineering Physics / Applied Physics | National University of Singapore | 2009 – 2013

•       Dissertation: "Layered Chalcogenide Nanostructures: Synthesis, Characterization, and Optoelectrical Applications" | Focus: Nanofabrication, device physics, optoelectronics, materials characterization

M.Sc., Physics (Nanoscience & Nanotechnology) | IIT Madras | 2007 – 2009

B.Sc., Physics | Ramakrishna Mission Residential College | 2004 – 2007

PATENTS (4 US Patents – Granted & Pending)

•       "Etching Processes and Processing Assemblies" — US Patent 12,322,575 (Granted 2025) & Application 19/206,137

•       "Methods and Assemblies for Depositing Material in a Gap" US Patent Application 18/754,246 (2025)

•       "Methods for Filling a Gap and Related Systems and Devices" —US Patent 12,027,365 (Granted 2024)

PUBLICATIONS & RESEARCH IMPACT

26+ peer-reviewed journal articles (16 as First/Corresponding Author) | 1,382+ citations | h-index: 17 | i10-index: 22

10 conference papers | 24 invited/regular presentations | Peer reviewer for 20+ manuscripts in Nature, ACS, RSC, IOP, Springer

Selected High-Impact Publications:

•       "Reaction Mechanism & Selectivity Control of Si-Compound ALE Based on Plasma Modification" — Langmuir (ACS), 37(43), 2021

•       "ReS₂/h-BN/Graphene Multifunctional Devices" — Advanced Electronic Materials, 7(1), 2021

•       "Laser-Assisted Multi-Level NVM Device Based on Few-Layer ReS₂" — Advanced Functional Materials, 30(42), 2020

•       "Enhanced Quantum Efficiency in n-ReS₂/p-Si Heterojunction Photodiodes"  ACS Photonics, 6(9), 2019

•       "Complex Electrical Permittivity of Monolayer MoS₂" — Optical Materials Express, 5(2), 2015

•       "NIR Schottky Photodetectors Based on GeSe Nanosheet" — ACS Applied Materials & Interfaces, 5(19), 2013 (272 citations)

Awards & Fellowships:

•       Ramanujan Fellowship (2022) — Department of Science & Technology, India — Prestigious national research fellowship

•       Research Highlighted in NIMS Press Release — Recognition of breakthrough 2D material-based memory device research

•       Excellent Poster Presentation Award (2019) — MANA International Symposium, Tsukuba, Japan

•       JSPS Postdoctoral Fellowship (2017) — Japan Society for the Promotion of Science — Highly competitive fellowship

•       MANA Postdoctoral Fellowship (2019) — National Institute for Materials Science, Japan

•       DAAD Research Scholarship (2009) — German Academic Exchange Service

•       Erasmus Mundus Scholarship (2009) — European Commission

PROFESSIONAL AFFILIATIONS & SERVICE

•       Technical Liaison — Semiconductor Research Corporation (SRC) | 2021 – Present

•       Member — Materials Research Society of Singapore, The Japan Society of Applied Physics (JSAP), The Optical Society of India

•       Peer Reviewer — 20+ manuscripts for Nature Communications, Applied Physics Letters, Scientific Reports, ACS journals, IOP, Springer | 2014 – Present

•       Mendeley Advisor — Elsevier | 2014 – Present | Technical Seminar Liaison — Micron Technology India | 2023 – Present

•       Conference Volunteer — International Conference on Emerging Electronics (ICEE 2016), IIT Bombay

TECHNICAL SKILLS & EXPERTISE

Design & Layout

NAND design rules, reticle integration, layout optimization, DFM, yield analysis, AI-assisted rule development

Verification Tools

Mentor Graphics Calibre (DRC/LVS/LVL/RVE/DRV), KLayout, hotspot analysis, layout-sensitive analytics

Process Technology

PEALD/PEALE, plasma etching, CVD/PVD/ALD, area-selective deposition/etching, gap-fill optimization, thin-film processes

Simulation & Analytics

TCAD device simulation, JMP (DoE), Python, MATLAB, advanced Excel, data analysis/visualization, statistical methods

Characterization

Ellipsometry, in-situ FTIR, XRD, XPS, Raman/PL, OES, Langmuir probe, SEM/TEM/AFM, electrical/optical characterization

Nanofabrication

Photolithography, e-beam lithography, device fabrication (FET/diode/photodetector/memory), 2D materials processing

KEY ACHIEVEMENTS & IMPACT

•       Established PDK and design rule infrastructure for 4 advanced 3D NAND nodes (176-200+ layers), enabling successful tapeout and production ramp.

•       Achieved 30-40% reduction in DRC violations through systematic analytics and root-cause analysis, accelerating tapeout convergence.

•       Maintained >95% on-time milestone delivery for PDK releases across multiple concurrent technology development programs.

•       Developed 4 US patents in plasma-enhanced etching and area-selective gap-fill deposition for advanced semiconductor manufacturing.

•       Published 26+ peer-reviewed articles with 1,382+ citations (h-index: 17), demonstrating sustained scientific impact and thought leadership.

•       Recipient of 5 prestigious international fellowships: Ramanujan (India), JSPS (Japan), MANA (Japan), DAAD (Germany), Erasmus Mundus (EU).

•       Led cross-functional teams across design, PI, lithography, and yield in multiple semiconductor companies spanning Asia, Europe, and North America.

•       Pioneered PEALE and area-selective processes for 3D NAND, achieving breakthrough improvements in selectivity and manufacturability.

•    Serve as SRC technical liaison bridging industry-academia collaboration and facilitating semiconductor technology roadmap development.