Industry Experience

PRESENT POSITION

08/08/2022 – Present                                        Micron Technology | Senior Engineer, Advanced NAND Technology (ANT)

 Technical aspects:

# NAND Design Rule/Process Integration Engineer.

# Top skills: Semiconductor Device • NAND Flash Memory • Design Rule • Process Integration Engineering • Cross-functional Team Leadership

NAND Design Responsibilities

• Responsible for NAND design rules and clean sheets.

• Worked closely with PI, photo, reticle, Design, and PE teams to define future technology nodes for all designs to reduce the number of reticles tapped out per design.

Reticle Creation and Verification

• Responsible for various steps involved in reticle creation for CMOS, Array, interconnect, and BEOL layers across NAND technology nodes in both R&D and Production.

• Involved in the definition, implementation, and verification of the CMOS and array.

Troubleshooting and Yield Improvement

• Heavily involved in troubleshooting various fab issues, especially layout-sensitive designs and yield loss-related design fixes.

• Created standalone DRCs to catch failing locations with the Design team and help increase yield with the YE team.

Simulation and Validation

• Responsible for requesting TCAD, structure, OPC, electrical, and Reliability simulations for Die database design edit requirements.

• Debugged test structure fail modes, including design rules validation and layout analysis to match specifications.

Team co-ordination:

# Co-ordinate the work of experienced engineers from Process Integration, Advanced Mask Design, Scribe & Frame, and Layout & Design to help direct development efforts for a new 3D NAND generation from early development until manufacturing ceases.

# Pro-actively identify and address process issues and process window vs. die size conflicts stemming from specific database layout or layout techniques.

Project responsibilities:

# Assure that the right DRC’s (Design Rule Checks) are in place, assure appropriate reaction to deviation from established design rules.

# Work with Yield Enhancement, Product Engineers, Defect analysis, Param, and Quality Assurance teams to understand process issues related to the database layout, and prioritize development of solutions with Process Integration, Advanced Mask Design, Scribe & Frame, Layout & Design.

# Help design and evaluate test structures to provide data for next generation devices, to quantify process margin on current devices.

Managerial Aspects:

# Maintain and enforce best possible communication between Process Integration, Product Engineering, Advanced Mask Design, Scribe & Frame, Layout & Design.

# Assure timely documentation of the R&D activities with regard to design rule improvements for transfer to parts still in design. 

# Manage cross-disciplinary projects on novel processes, personnel, schedules and plans. Communicated with all organization levels in a global environment, addressing issues.

PAST Experience

14/09/2020 – 31/07/2022               ASM International N.V. | Senior Process Engineer, CRD            https://www.asm.com/                       

# This position is based in ASM’s Corporate R&D research group collaboration with Nagoya University Japan. 

# Works with semiconductor processing equipment to research, develop and optimize plasma enhanced processes.

# R&D at new process development group working on development of atomic layer etching & area-selective deposition processes in a single reactor. Characterization, in-situ analysis, continuous improvement for future technology.

# Process development of plasma assist deposited films, gap-fill films for logic, flash memory, DRAM and MOSFET applications.

# Delivers creative solutions, creates inventions and develops intellectual property.

# University Collaboration (Managerial Aspects)

# Joint development projects (JDPs) with largest plasma science center, team lead

# Technology development support via process transfer & learning implementation

TECHNICAL SKILLS & HIGHLIGHTS

Experimental Skill: 

# Lithography techniques: Electron beam lithography (EBL), Laser lithography, Photo-lithography

# Thin film fabrication: Sputtering, CVD, PECVD, Atomic layer deposition (ALD), Atomic Layer Etching (ALE), e-deposition

# Imaging: Scanning microscope (SEM, TEM, STEM), AFM

# Spectroscopic analysis: In-situ Ellipsometer, In-situ FTIR, IR-RAS, XRD, XPS, micro-Raman & PL, Reflectance spectroscopy

# Plasma diagnostics: OES (Andor, Ocean Optics), retarding field energy analyser (R.F.E.A.), Langmuir probe

Electrical and Optoelectrical measurement techniques:

# Electrical characterization (I-V, I-time, C-V, C-f, I- Pulsed V, Hall measurement). Locally probe scanning measurement.

# Optoelectrical measurements using electro-optic modulator preamplifier and lock-in amplifier.

# Equipment (Electrical test, Oscilloscopes, Signal Generators, Logic & Memory Analyzers).

Simulation & Designs Tool:

# Optical Wavenology-3D EM, Lumerical FDTD, CST studio; Device: Lumerical Device, Optoelectronic TCAD, Design CAD

# Cadence Virtuoso: design layout; Design Rule Check DRC (K layout, Calibre)

Analysis tool: Matlab, Python data analysis, JMP 15.1, and Plotting tool: Origin, XPS peak fit 4.1

Process Development:

# Dry-etching techniques: Usual continuous & discontinuous plasma (pulsing), remote plasma, vapor phase etching with radicals & ions, evaluation of an implantation & isotropic removal technique.

Short Bio:

B. Mukherjee received M.Sc. and Ph.D. in Physics specializing in Materials Science and Engineering from IIT Madras and National University of Singapore (NUS) in 2009 and 2013, respectively. He joined Micron as a Senior Design Rule Engineer working with NAND Technology Integration (NTI) and Advanced NAND Technology (ANT) team members. Prior to joining Micron, he was working as a senior process engineer in ASM International. He is actively participating in advanced nodes RG NAND cell, design improvement activities to enhance process margin, enable low cost process and continuous yield improvement projects. He awarded DAAD fellowship from Germany in 2009, JSPS fellowship from Japan in 2019 and Ramanujan Fellowship from India in 2020. He has authored ~ 22 articles, co-authored ~16 articles, 1 book chapter and filled 3 patents.