Publications

Selected Journal Publications

1. M. A. Chowdhury, R. Zand, and S. Salehi, “Dyn-A-Map: Dynamic AI-Model Mapping for robust and accurate MRAM-based analog edge computing,” npj Unconventional Computing, vol. 3, Art. no. 27, June 2026, doi: 10.1038/s44335-026-00072-6.

2. H. K. Dharavath, B. S. Latibari, K. I. Gubbi, M. A. Chowdhury, S. Ghimire, R. Yasaei, P. Satam, A. Sasan, H. Homayoun, and S. Salehi, “Stealthy Hardware Trojans in AI Accelerators: Attacks on Transformer, Convolutional Neural Network, and Systolic Architectures,” IEEE Micro, vol. 46, no. 3, pp. 88–98, May–June 2026, doi: 10.1109/MM.2026.3687478.

3. S. Ghimire, Y.-Z. Lin, M. Mamun, M. A. Chowdhury, F. Alemi, S. Cai, J. Guo, M. Zhu, H. Li, B. S. Latibari, S. Rafatirad, P. Satam, and S. Salehi, “HWREx: AI-enabled Hardware Weakness and Risk Exploration and Storytelling Framework with LLM-assisted Mitigation Suggestion,” ACM Transactions on Design Automation of Electronic Systems, vol. 30, no. 6, Art. no. 104, pp. 1–33, Oct. 2025, doi: 10.1145/3737459.

4. M. A. Chowdhury, M. Hossain, C. Mastrangelo, R. F. DeMara, and S. Salehi, “S-Tune: SOT-MTJ manufacturing parameters tuning for securing the next generation of computing,” Frontiers in Electronics, vol. 5, Art. no. 1409548, Aug. 2024, doi: 10.3389/felec.2024.1409548.

5. K. I. Gubbi, B. S. Latibari, M. A. Chowdhury, A. Jalilzadeh, E. Y. Hamedani, S. Rafatirad, A. Sasan, H. Homayoun, and S. Salehi, “Optimized and Automated Secure IC Design Flow: A Defense-in-Depth Approach,” IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 71, no. 5, pp. 2031–2044, May 2024, doi: 10.1109/TCSI.2024.3364160.

6. B. S. Latibari, N. Nazari, M. A. Chowdhury, K. I. Gubbi, C. Fang, S. Ghimire, E. Hosseini, H. Sayadi, H. Homayoun, S. Salehi, and A. Sasan, “Transformers: A Security Perspective,” IEEE Access, vol. 12, pp. 181071–181105, 2024, doi: 10.1109/ACCESS.2024.3509372.

7. A. Fahim, M. Hasan, and M. A. Chowdhury, “Smart Parking Systems: Comprehensive Review based on various aspects,” Heliyon, vol. 7, no. 5, Art. no. e07050, 2021, doi: 10.1016/j.heliyon.2021.e07050.

8. M.-S. Hossain, M. A. Chowdhury, and M. S. Rahman, “A dual reduction strategy for reduce-order modeling of periodic control system,” Results in Control and Optimization, vol. 4, Art. no. 100034, 2021, doi: 10.1016/j.rico.2021.100034.

Selected Conference Publications

1. H. Gibbs, M. A. Chowdhury, V. Pugazhenthi, P. Mirfasihi, S. Ghimire, X. Ramus, S. Shao, R. Yasaei, P. Satam, and S. Salehi, “LEAKI-PLC: Live End-to-End AES Key Recovery from Industrial PLCs via Electromagnetic Side-Channel Analysis,” 2026 IEEE International Conference on Physical Assurance and Inspection of Electronics (PAINE), 2026. Accepted.

2. M. A. Chowdhury, R. Zand, and S. Salehi, “ARMOR-IMC: Adaptive Resource Mapping for Operational Robustness via Secure In-Memory Computing,” 2026 IEEE International Conference on Omni-Layer Intelligent Systems (COINS), 2026. Accepted for presentation. Preprint: arXiv:2607.10938.

3. V. Pugazhenthi, M. A. Chowdhury, S. Ghimire, H. K. Dharavath, P. Mirfasihi, N. Sehatbakhsh, P. Satam, and S. Salehi, “LeakSEAL: Power Side-Channel Leakage Analysis and Mitigation for Secure Edge AI Learning,” Proceedings of the Great Lakes Symposium on VLSI 2026 (GLSVLSI '26), pp. 135–140, 2026, doi: 10.1145/3787109.3816388.

4. S. Ghimire, P. Mirfasihi, M. A. Chowdhury, V. Pugazhenthi, H. K. Dharavath, F. Firouzi, R. Yasaei, P. Satam, and S. Salehi, “Can Agents Secure Hardware? Evaluating Agentic LLM-Driven Obfuscation for IP Protection,” 2026 IEEE 44th VLSI Test Symposium (VTS), pp. 1–5, 2026, doi: 10.1109/VTS69484.2026.11563377.

5. V. Pugazhenthi, M. A. Chowdhury, S. Ghimire, H. K. Dharavath, B. S. Latibari, and S. Salehi, “Power Side-Channel Leakage Assessment of FPGA-Based Spiking Neural Networks,” 2025 IEEE 68th International Midwest Symposium on Circuits and Systems (MWSCAS), pp. 588–592, 2025, doi: 10.1109/MWSCAS53549.2025.11244502.

6. L. Fehlings, M. A. Chowdhury, B. S. Latibari, S. Salehi, and E. Covi, “Reliability of Capacitive Read in Arrays of Ferroelectric Capacitors,” 2025 IEEE International Symposium on Circuits and Systems (ISCAS), London, United Kingdom, 2025, pp. 1–5, doi: 10.1109/ISCAS56072.2025.11044070.

7. S. Ghimire, M. A. Chowdhury, R. Tsang, R. Yarnell, E. Heckert, J. Carpenter, Y.-Z. Lin, M. Mamun, R. F. DeMara, S. Rafatirad, P. Satam, and S. Salehi, “Interactive Framework for Cybersecurity Education and Future Workforce Development,” 2024 IEEE Frontiers in Education Conference (FIE), pp. 1–7, 2024, doi: 10.1109/FIE61694.2024.10892909.

8. B. S. Latibari, S. Ghimire, M. A. Chowdhury, N. Nazari, K. I. Gubbi, H. Homayoun, A. Sasan, and S. Salehi, “Automated Hardware Logic Obfuscation Framework Using GPT,” 2024 IEEE 17th Dallas Circuits and Systems Conference (DCAS), pp. 1–5, 2024, doi: 10.1109/DCAS61159.2024.10539877.

9. M. Hossain, M. A. Chowdhury, R. F. DeMara, and S. Salehi, “Sensitivity Analysis of SOT-MTJs to Manufacturing Process Variation: A Hardware Security Perspective,” 2024 25th International Symposium on Quality Electronic Design (ISQED), San Francisco, CA, USA, 2024, pp. 1–5, doi: 10.1109/ISQED60706.2024.10528782.

10. N. Nazari, K. I. Gubbi, B. S. Latibari, M. A. Chowdhury, C. Fang, A. Sasan, S. Rafatirad, H. Homayoun, and S. Salehi, “Securing On-Chip Learning: Navigating Vulnerabilities and Potential Safeguards in Spiking Neural Network Architectures,” 2024 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1–5, 2024, doi: 10.1109/ISCAS58744.2024.10558041.

11. R. C. Yarnell, M. Hossain, R. Graterol, A. Pindoria, S. Ghimire, M. A. Chowdhury, S. Salehi, Y. Bai, and R. F. DeMara, “Educational Tool-spaces for Convolutional Neural Network FPGA Design Space Exploration Using High-Level Synthesis,” Proceedings of the Great Lakes Symposium on VLSI 2024 (GLSVLSI '24), Clearwater, FL, USA, pp. 343–346, 2024, doi: 10.1145/3649476.3658786.

12. S. Chowdhury, A. Chakraborty, U. b. Joy, A. Fahim, M. A. Chowdhury, and M. Hasan, “A 60 GHz and 2.08 mW Active Quasi-Circulator in 22 nm FDSOI Technology,” 2023 IEEE 66th International Midwest Symposium on Circuits and Systems (MWSCAS), Tempe, AZ, USA, 2023, pp. 684–688, doi: 10.1109/MWSCAS57524.2023.10405923.

13. M. A. Chowdhury, M. A. Mona, A. Al Asif, M. Nayem, M. A. Z. Dipto, and A. Sorwar, “Performance Comparison of Full Adder Cells in 45nm Technology Node,” 2021 International Conference on Computer Communication and Informatics (ICCCI), 2021, pp. 1–5, doi: 10.1109/ICCCI50826.2021.9402506.

14. A. Fahim, M. A. Chowdhury, M. F. Alam, F. Elahi, E. C. Shourov, and M. Hasan, “Smart Transformer Theft Protection and Maintenance Monitoring System,” 2021 2nd International Conference on Robotics, Electrical and Signal Processing Techniques (ICREST), 2021, pp. 607–612, doi: 10.1109/ICREST51555.2021.9331157.

15. M. S. Hossain, M. A. Chowdhury, and M. S. Rahman, “A structured Krylov subspace approach based model reduction of periodic control system in lifted form,” 2021 6th International Conference on Inventive Computation Technologies (ICICT), 2021, pp. 257–262, doi: 10.1109/ICICT50816.2021.9358796.

16. M. A. Chowdhury, K. A. Faieq, T. B. Khalid, and S. Siddique, “ExoArm: Patient Rehabilitation, Mobility and Heavy-lifting using COTS Components,” 2020 11th IEEE Control and System Graduate Research Colloquium (ICSGRC), 2020, pp. 82–87, doi: 10.1109/ICSGRC49013.2020.9232559.

17. T. B. Khalid, M. A. Chowdhury, and K. A. Faieq, “Near-field Communication enabled Voice and Touch integrated Home Automation for Elderly and Disabled,” 2020 IEEE Region 10 Symposium (TENSYMP), 2020, pp. 1193–1196, doi: 10.1109/TENSYMP50017.2020.9230978.

Preprints

1. H. K. Dharavath, M. A. Chowdhury, R. Yasaei, and S. Salehi, “LIB-TRAP: Standard Cell Library Hardware Trojan Risk Assessment and Prevention,” arXiv preprint arXiv:2607.01526, July 2026, revised Aug. 2026.

2. S. Ghimire, P. Mirfasihi, M. A. Chowdhury, H. K. Dharavath, B. S. Latibari, M. Mamun, J. W. Carpenter, B. Tan, H. Pearce, K. Chakrabarty, P. Satam, and S. Salehi, “Large Language Models and Attention-Based AI for Hardware Design and Security: Progress, Challenges, and Opportunities,” arXiv preprint arXiv:2504.08854, Apr. 2025, revised July 2026.

Book Chapters in Preparation

1. S. Ghimire, P. Mirfasihi, M. A. Chowdhury, V. Pugazhenthi, H. K. Dharavath, K. I. Gubbi, H. Homayoun, R. Yasaei, P. Satam, and S. Salehi, “Hardware Design Leveraging LLMs: From IP to SoC,” Chapter 3. In preparation.