Traditional CMOS (Complementary Metal Oxide Semiconductor) scaling has become increasingly difficult, especially over the course of the last decade. This is mainly due to the rising costs of development as ever smaller gate lengths have led to more complex SCEs. Many people believe that it is a technological limit which slows down or stops Moore’s Law. However, this is simply not true. As Gordon Moore said himself, “Moore’s Law is really about economics”. As long as there is demand for faster, more power efficient semiconductors, technological progress will continue.

Even though demand for semiconductors has been rising, the rising costs of development have eclipsed the capabilities of many foundries. Thus, there are only four companies which plan to continue their efforts in scaling down transistors. These companies are Intel, TSMC, Samsung and Globalfoundries. However, the latter is an example of how even these large companies are struggling in an era of post-Dennard scaling.

In early 2018, Globalfoundries installed two new EUV machines at its Fab 8 facility in an effort to keep pace with the competition. However, soon after, in mid-2018, it decided to halt its plans to move to the new 7 nm node and the use of EUV. The investors were considering selling the EUV machines as they tried to maintain profitability over innovation. This signalled the start of a fall in year-to-year growth in computing power, but also marked the path which the industry will likely take in the next few years.

It shows that in the short-term, growth will not be sustained primarily by the shrinking of transistors. Instead, growth will be facilitated by a greater focus on parallel CPU architecture and advancements in specialised silicon. The demand for chips which have a specific purpose, e.g: those to be used to power neural networks or manage vast server farms, will rise. The focus on increases parallelism will drive the CPU core count upwards and the demand for HBM memory will increase as there will be a shift in how memory and compute are integrated.

Although the growth in profits for these companies has fallen, they still manage to turn large profits every year. For example, TSMC was responsible for manufacturing 7 nm chipsets for Apple and Huawei in the iPhone Xs and the Huawei Mate 20 Pro. In a remark made by TSMC in 2018, it is confident that scaling will continue down to 3 and 2 nm, showing that the hurdles to Moore’s Law are economic, not technological.

Furthermore, SEMI’s World Fab Forecast reinforces the strength of the semiconductor market. It forecasts that investment in new fabrication technologies will grow 14% to $62.8 billion annually, with investment in research growing to $17 billion. However, the increased cost of research and manufacturing is countered by the ever increasing demand for silicon. Q3 2018 silicon wafer area shipments increased 3% on Q2 2018 to set another all-time high, according to the SEMI Silicon Manufacturers Group (SMG). It was also 8.6% higher than the same time in 2017. All of this data shows that there is incredibly strong demand for further innovation within the semiconductor industry. Since Moore’s Law is driven by economics, this reinforces the idea that we will not see a significant slow down in the growth of computational power. So, if transistors cannot be shrunk, what are the alternative methods and which will most likely succeed?

As the difficulty of scaling rises, companies are taking longer durations between major architectural revisions. However, investment into parallelisation has dramatically increased. In early June of 2019, AMD announced its new Ryzen 3000 series of processors, truly bringing high core-count processing to the general public. For example, the Ryzen 9 3900X brings 12 cores and 24 threads to the general consumer for a price of $499. These high core-counts were previously only reserved for enterprise customers, often also requiring the use of specialised hardware such as custom motherboards and cooling solutions.

Ryzen 9 is based on the new Zen 2 architecture, which emphasizes the use of chiplets. Consequently, the die on the new AMD processors consists of a combination of chiplets from a variety of vendors. For example, the IO is separated from the “Core Complex” (also known as CCX) of the processor. The CCX is itself comprised of four cores. The IO must communicate with the CCX in a fast and efficient manner. Here is where AMD’s infinity fabric comes into play, announced in April of 2017, which allows the connection of the CCX with a plethora of different chipsets.

It is important to note that it is not just AMD which is driving the use of chiplets. Intel, the largest manufacturer of desktop semiconductors, also has plans to join the chiplet revolution.

After spending years in development and millions in development costs, Intel believes that its approach is finally ready for production. It’s called the Embedded Multi-Die Interconnect Bridge, or EMIB, for short. It comprises of a high-density bridge which connects the individual chiplets together. A silicon interposer brings all the individual chiplets together in order to package the substrate. (A silicon interposer is a silicon substrate with dense interconnects and TSVs (Through Silicon Vias) built into it. These allow for high bandwidth connections.) The high density interconnects on the silicon substrate are called microbumps (as named by Intel). Intel says that they provide a higher density than standard packaging substrates. Using this new technology will be costly, so Intel plans to use it only where it is needed, localising it to particular areas on the die.

To demonstrate the viability of EMIB, Intel has already made some products commercially available which are powered by this technology. A prominent example is Kaby Lake-G. It represents a partnership between Intel and AMD, for the integration of an AMD GPU, along with HBM and Intel’s CPU. More interestingly, a HMB interface was used for the HBM in the package, whereas PCI-E (a standard circuit board level interface) was used within the package for the CPU and GPU integration, both industry standards. The use of standard interfaces shows that Intel is actively encouraging the shift to a fabless industry, where the cost of chip development can be dramatically lowered.

Along with the cost reductions which Intel desperately needs to compete today, having a chiplet arrangement like the one in Kaby Lake-G, allows chip designers to focus solely on their strengths and overcome their weaknesses by partnering with other chipset designers. The reason why AMD built the GPU and Intel the CPU for this product is because these are the components which the other company is better at designing and building. This project was simply a testing ground for future partnerships between the two companies, which could lead to a much better product for the consumer in the end. As a result, EMIB is able to benefit both the consumer which uses, the companies which design and the foundries which manufacture the chips.

Today, the major chipset vendors have a choice to make. They could either continue down the path of traditional CMOS scaling, where the pitch of the transistors is made ever smaller, or start a revolution. A shift in not only how chips are developed and manufactured, but also how business itself is conducted within the industry. In an ideal world, both options would be pursued to their fullest extent. However, in the real world, even the largest companies have limited resources for research and development. So, a firm decision has to be made.

Choosing the first option provides a predictable path for the next half a decade. It is a relatively safe option, since although scaling is becoming more of a challenge, both from an economic and scientific perspective, these companies have decades worth of experience regarding performance enhancements from scaling. The improvements to power consumption and efficiency can be easily and accurately predicted, making the creation of a roadmap quite easy.

However, choosing this path will lead to imminent stagnation, which would truly slow down Moore’s Law after five years. Even if the majority of research and development resources were poured into scaling, eventually a hard wall would be hit. With no other technology to replace it, this relatively safe option becomes one of unsustainable growth. Hitting a dead-end in performance growth would have disastrous consequences for all sectors of society, not just the semiconductor industry, since almost all sectors are reliant on computation and hence computational growth.

The second option is unpredictable, but boundless in terms of potential. Firstly, it will allow for growth to continue well past the decade mark. Currently, we are only seeing the results of small experiments with chiplets. In the near future, it is almost certain that logic-to-logic integration on a 3D level will become possible. Extending the die into 3D space will allow for chip designs never possible before and a rate of growth never witnessed. Furthermore, it provides a path into the future where silicon is not the primary semiconductor. This modular architecture would allow the integration of traditional CMOS with Beyond CMOS technologies.

The use of chiplets will also be a catalyst for innovation and collaboration between companies. For example, specialised hardware for growing fields such as machine learning would be much easier to construct and maintain, in addition to being orders of magnitude faster than anything available today, or with traditional scaling in the future. The barriers to entry into the semiconductor industry will be greatly lowered as a foundry is no longer required, increasing competition which would increase quality and reduce prices. In addition to this, chiplets promote IP (Intellectual Property) reuse, hugely reducing the research and development costs for chip design as the architecture does not have to be built from scratch. As highlighted previously, reducing these costs will be key if Moore’s Law is to continue.

Even though chiplets provide the potential for a bright future, they too have hurdles to overcome. Currently, as stated by Intel, the use of chiplets is still relatively expensive. This is a barrier which will definitely be overcome and in some ways has already been. With AMD bringing its Ryzen 3000 series, it not only brings 7 nm to the consumer, but also its Infinity Fabric, an interconnect architecture similar to EMIB (but proprietary).

The larger barrier to EMIB is having a universal standard across the industry. For example, although chiplets have the potential to increase yield, they can actually cause problems reducing yield too. For example, without a universal standard test to verify quality, if only one of chiplets is not functional and is used in the package, all the other good chiplets will also become useless. Furthermore, vendors must do more to have better support for power and thermal management, so sufficient information is provided by each individual chiplet in order to manage the power and thermals correctly. This is especially important in the future with 3D stacking where the confined spaces for chiplets in the middle provide a large challenge for heat dissipation. Finally, a mechanical standard for the placement of the microbumps is also needed, to increase compatibility across vendors.

Investment solely in chiplets is not viable either. This is because although chiplets can provide increases in performance, the primary source for increase in efficiency is still through traditional scaling. As a result, I believe that there must be investment in both scaling and chiplets, but there should be a greater focus on the development of chiplet-based technologies until the materials to replace silicon are perfected.