Isolating a monatomic layer of carbon was a quest for scientists for well over a century, with attempts which date back to 1859. However, since the discovery of graphene in 2004 by Professor Sir Andre Geim and Professor Sir Kostya Novoselov, interest in 2D materials has seen an explosive rise. The unique electrical, thermal, mechanical and optical properties of many 2D materials, not just graphene, have made them ideal for a large variety of applications such as: catalysing chemical reactions; supercapacitors, batteries and other energy storage devices; high performance-sensors and for building electronic devices.

It is commonly known that 2D materials exhibit phenomenal electrical conductivity. This is, in part, due to great charge carrier mobility within their layered structures. Crystalline silicon, for example, has an electron mobility of 1,400 cm²/Vs at room temperature. In contrast, a report in 2004 showed that the field-effect mobility of electrons in graphene on silicon dioxide was 10,000 cm²/Vs, an order of magnitude greater. It was predicted that a theoretical maximum of 40,000 cm²/Vs could be achieved, if the electron scattering effects could be better managed. However, through the use of suspended graphene, this figure was pushed to 120,000 cm²/Vs and then an extraordinary 1,000,000 cm²/Vs at 240K. Since the charge carrier’s velocity is proportional to the carrier mobility of the conducting material at low electric field strengths, by having a higher charge carrier mobility, electrons (and holes) can travel from source to drain faster, increasing the frequency of operation of the transistor (or clock-speeds) and thus increasing the performance of the transistor by orders of magnitude. 2D materials promise to not only carry on Moore’s Law, but also spark a return back to Dennard Scaling, where clock speeds increase exponentially.

MOSFET scaling with traditional Si-based CMOS has resulted in cost reductions, greater performance as well as better energy efficiency. However, as we have continued rapid scaling, in order to progress to the next node, the challenges have risen. Over time, many of the “traditional” CMOS elements have been succeeded by more modern alternatives and developments. For example the SiO₂ gate oxide has been replaced with high-K dielectric materials and the planar MOSFET as been replaced with 3D FinFET. This has led many to believe that the concept of silicon itself as the predominant semiconducting material should be abandoned. 2D materials are much easier to scale than traditional 3D materials such as bulk silicon. Since 2D materials are layered, taking a single layer out of their bulk state does not degrade their properties. However, doing the same with 3D materials yields unfavourable outcomes. Thus, 2D materials, by nature, offer ease of scaling down device dimensions, helping to reduce power consumption too.

2D materials sound phenomenal for use in FETs; they improve performance, while lowering power consumption and overall size. However, as extensive research has been conducted on them in the past decade, challenges involving synthesis and parasitic properties have risen - two tremendous obstacles for this novel class of materials, but can they overcome these to replace silicon?

For a few researchers, the search for the ideal semiconductor succeeded almost two decades ago, in 1991, with the discovery of carbon nanotubes by Sumio Iijima. Their ultrathin bodies, brilliant electron and hole transport properties and a reasonable energy band-gap of 0.6 to 0.8 eV give CNTs tremendous potential to be scaled well below 10 nm node. CNTs are a very peculiar kind of semiconductor. Unlike the silicon commonly found today or even germanium, which was used in the early days of the transistor, CNTs are intrinsic semiconductors. As a result, the number of charge carriers is determined by the material itself, rather than the concentration of dopants added into the parent material. Thus, CNTs do not need to be doped in the traditional way silicon or germanium have to be. This would greatly reduce device variability while manufacturing on a large scale at tiny device dimensions. Furthermore, no inversion layer of charge is formed. Instead the field from the gate electrode can directly alter the material’s properties to allow for the flow of charge carriers from source to drain, through the carbon nanotube, allowing the CNT-based device to operate at a frequency much higher than a traditional FET, leading to far greater performance.

NEM switches use electrostatic forces to actuate a physical structure to control the flow of current. They act much like a traditional switch by creating a physical gap between two conductive electrodes to turn off the current and create the OFF state. They contacts are brought together to create the ON state. They have two main properties which make them completely different to conventional FETs. They have zero leakage current, leading to extreme electrical and thermal efficiency and zero subthreshold swing, creating a higher ON/OFF ratio. The gate is also ambipolar, allowing a positive or negative voltage polarity. Furthermore, they can work at a huge temperature range, since they do not rely on any carrier transport properties of a material which change with the operating temperature, allowing such a device to operate in very harsh conditions. They are also immune to ionising radiation and inexpensive substrates such as glass or plastic can be used to fabricate them.

The key to increasing transistor efficiency while scaling is to increase electrostatic control over the channel. This is achieved through the reduction of SCEs. As a result, the subthreshold swing of the transistor is decreased. The subthreshold swing, typically measured in mV/decade, is simply the voltage required to achieve a ten times increase in drain current (the subthreshold slope is the inverse of the subthreshold swing and is consequently measured in decade/mV). A lower subthreshold swing contributes to a higher ION/IOFF ratio. Thus, leakage current is reduced and the transistor’s efficiency is increased.

As conventional Si-CMOS devices have been shrunk, control over SCEs has decreased. As a result, subthreshold swings have hit a hard limit at around 60 mV/decade and cannot be easily reduced even with more complex geometries such as FinFET and nanowire (Gate-All-Around) FETs. However, TFETs may be able to change that with experimental devices reaching subthreshold swings of just 3.9 mV/decade. Although these transistors are not explicitly made for high performance or high speed computing, like NEMs, they are incredibly useful in IoT and data centre applications where energy and thermal efficiency, not performance, are priorities. This is an essential technology for reducing total energy consumption, greenhouse gas emissions and reducing the impacts of climate change. Datacentres, for example, consume 3% of the world’s total energy supply and produce 2% of the world’s total greenhouse gas emissions. Last year, they consumed 416.2 TWh of energy - far higher than the UK’s total energy consumption.

The III-V stands for the groups of the periodic table from which the elements form the compounds required for the silicon channel replacement. The motivation behind the development of III-V Channel Replacement Devices is similar to that of the use of 2D materials and CNTs. They combine high carrier mobility, low contact resistance and sufficient interfacial quality with high-K dielectrics and adequate band gap energy to form, in theory, the ideal replacement to the silicon currently used. However, unlike the technologies previously discussed, the type of the transistor determines which channel material should be used. For n-type MOSFETs (where free electrons are the majority charge carriers), InGaAs and for p-type MOSFETs (where holes are the majority charge carriers), InGaSb are the focus in the field of III-V materials. Both types of MOSFETs are needed to form the seven logic gates: AND, OR, XOR, NAND, NOR, XNOR and NOT. These logic gates form the basis of all “conventional” computing.

For the past few decades and much of the history of the computer, the main way to increase computational power has been to increase the number of transistors. By making transistors smaller, we have allowed their density to explode. Thus more transistors can fit onto the same die area. However, as shrinking the transistors becomes more difficult, researchers have started to explore the third dimension. Through extension of transistor density from the current 2D plane into a 3D structure, performance increases of orders of magnitude can be achieved, all at the same node, bypassing the need for smaller transistors to some extent.

Although this technology will yield greatly increased performance, gains in efficiency will still primarily come from the shrinking of transistors. However, this does not mean that 3D architectures offer no new efficiency advantages. For example, 3D architectures could bring DRAM much closer to the transistors themselves. Since data is transferred over a vastly shorter distance, not only is performance increased, but efficiency too as far less energy is used in the movement of data and chip-to-chip interconnect bottlenecks are reduced.

3D technologies hold tremendous potential for the near future, especially because they have already revolutionised the field of memory with the rise of Solid State Drives (SSDs). Mass volume production of 3D products started back in 2013 with Samsung and it’s V-NAND flash memory. Since then, continued advancements regarding memory density, speed, reliability and tumbling of SSD prices, have caused SSD adoption erupt to a predicted 60-65% in 2019, with even faster PCIE SSDs perhaps reaching 50% market penetration. 3D logic devices are expected to follow a similar trend if they were to become a reality.