The time period leading up to 2030 will likely be relatively calm and uninteresting. As 2030 approaches, the scaling potential of Si-CMOS will reach its absolute limit, even with VGAA technology. Thus, we will start to see the implementation of beyond CMOS technology, where silicon is replaced. By this time, it is expected that nanowire technology has been perfected with silicon and III-V material may finally be ready. Thus, the two will probably be combined to form III-V compound semiconductors. This will primarily increase charge carrier flow, leading to higher operating frequencies, increasing computational power.

Shortly after 2030, the potential of 3D TSV will have been most likely reached, as more layers simply cannot be stacked on top due to spatial and thermal limitations as a result of the thickness of the layers and low TSV density. By this time, monolithic 3D technology should be a cost effective alternative to 3D TSV, since bottom-up manufacturing techniques should be mature as GAA technology is widespread. Monolithic 3D will greatly increase the number of layers present, massively increasing transistor density.

During this period, although high performance computing may not see dramatic change, low performance-high efficiency computing will see two new technologies: NEMs and TFET/SE-TFET. The node size for the year 2030 is expected to be around 1.5-2 nm. At this length, I believe that NEMs simply cannot match the raw switching speed and therefore performance of TFET. However NEMs may still be an incredibly important technology since it will be one of the only computational technologies to withstand environmental conditions such as ionising radiation. With NASA planning to send humans to Mars in the year 2030 and private companies such as SpaceX building permanent residences on Mars around the same timeframe, NEMs maybe key to building computer systems capable of surviving the harshest of conditions.

The quantity of data collected is growing exponentially and is thus predicted to reach an estimated 175 zettabytes by just 2025. TFETs will be useful in the storage, retrieval and management of the huge quantities of data which will be collected due to the rise of IoT and technology giants as well as our governments continuing to collect vast sums of information about our daily activities. TFETs are the only viable low power solution due to their ability to utilise the otherwise detrimental quantum effects such as quantum tunneling which happen as gate length approaches 1 nm.

From the period between 2035 and 2040, the need for sub-nanometer technologies may become apparent. For high performance solutions, there may be no better alternative than CNT FETs. Due to the superb quantum confinement effects and carrier transport properties exhibited by CNTs, they may be the only way to avoid worsening SCEs and extend performance further through scaling. By this time, CNTs should be easily manufactured in large quantities with great yields; their manufacturing difficulty is one of the greatest hurdles holding them back today. Other parts of the transistor may also be replaced by graphene, TMDCs or other 2D materials. Beyond 2040, classical computing as a whole may no longer be able to cope with the computational needs of the world.