Experiences

☞ CPU Physical Design Engineer

Period: January 2023 to Present

E-Core (ATOM) Physical Design Automation,

Intel Corporation,

Austin, TX, USA.

Website: https://www.intel.com/content/www/us/en/homepage.html

Key Responsibilities:

- Successfully signed-off CPU cores for 4 SoCs: Meteor Lake (Intel 4), Sierra Forest (Intel 3), Arrow Lake (Intel 20A), Lunar Lake (TSMC N3).
- Owning and maintaining the power analysis flows and methodologies starting from RTL to backend (sign-off).
- Restructured the legacy sign-off power flow to improve efficiency and faster power rollup.
- Driving signal mapping improvements during physical synthesis which lead to ~98% signal coverage for accurate activity-based power analysis.
- Pioneered the new RTL power flow allowing early feedback to the RTL owners to fix/enhance the RTL long before physical synthesis.
- Developed the regression framework for power flow.
- Identified several tool bugs in commercial EDA tools which resulted in major EDA tool fixes.
- Helped develop power-characterization of custom IPs such as memories.

Skills & Expertises: click here

Intel and the Intel logo are trademarks of Intel Corporation or its subsidiaries.

☞ Graduate Research Assistant

Period: April 2019 to 2022

Warren B. Nelms Institute for the Connected World,

University of Florida,

Gainesville, FL, USA.

Website: http://iot.institute.ufl.edu/

Key Responsibilities:

- Working on implementation of different combinational and sequential hardware obfuscation methodologies in ASICs.
- Collaborating with Government, Industry, and Academia to explore the issues related to hardware security.
- Maintaining project deadlines by productive generation of research and research oriented activities.
- Mentoring students (undergraduate, graduate and doctoral) for their research projects.
- Attending conferences and meetings.
- Writing scientific and technical articles.

Skills & Expertise: click here

☞ EDA & Hardware Design Intern

Period: May 2021 to December 2021

Intel Corporation

Programmable Solutions Group (PSG), CTO Office

San Jose, CA, USA.

Website: https://www.intel.com/content/www/us/en/homepage.html

Key Responsibilities:

- Designing configurable logic (like look-up table) using ASIC.
- Synthesis and timing analysis of designs using commercial standard cell library.
- CAD tool support for IP design.
- Setting up regression frameworks and performing regression tests.
- Supporting integration of modules in SoC.

Skills & Expertise: click here

Intel and the Intel logo are trademarks of Intel Corporation or its subsidiaries.

☞ Graduate Research Assistant

Period: January 2018 to March 2019

Florida Institute for Cyber Security (FICS) Research,

University of Florida,

Gainesville, FL, USA.

Website: http://fics.institute.ufl.edu/

Key Responsibilities:

- Working on implementation of different combinational and sequential hardware obfuscation methodologies in ASICs.
- Collaborating with Government, Industry, and Academia to explore the issues related to hardware security.
- Maintaining project deadlines by productive generation of research and research oriented activities.
- Attending conferences and meetings.
- Writing scientific and technical articles.

Skills & Expertise: click here

☞ Lecturer of Electrical & Electronic Engineering (EEE)

Period: September 2016 to December 2017

Department of Computer Science & Engineering (CSE),

Southeast University (SEU),

Dhaka, Bangladesh.

Website: https://seu.edu.bd/

Key Responsibilities:

- Conducting theory and lab courses of undergraduate studies related to the area of EEE.
- Exam duties: Question paper set up, Invigilation, Answer script checking.
- Academic advising of undergraduate students.
- Supervising undergraduate thesis students.
  - Former thesis students :
- Attending seminars, conferences and administrative meetings.
- Mentoring Men's Soccer Team and organizing departmental programs (orientation, annual picnic, etc.).

☞ Miscellaneous

Lecturer of Physics & ICT : In a leading elementary academics coaching center used to teach Physics & Information and Communication Technology (ICT) in high school level classes.
Scouting : Served as a scout for 6 years at a stretch for the scout group of the high school. Was selected for the ranks of Senior Sixer & Senior Patrol Leader (SPL) for showing better efficiency in teamwork, leadership, etc.
Team Captain : Was an active player and the captain of the University Soccer team & Cricket team.

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