Md Moshiur Rahman, Ph.D.
Md Moshiur Rahman, Ph.D.
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CPU Physical Design Engineer
CPU Physical Design Engineer
Welcome to the personal webpage of Md Moshiur Rahman. Moshiur is a CPU Physical Design Engineer at Intel Corporation.
Welcome to the personal webpage of Md Moshiur Rahman. Moshiur is a CPU Physical Design Engineer at Intel Corporation.
He graduated with a PhD from the Department of Electrical and Computer Engineering (ECE) at University of Florida (UF), USA. He worked as a Graduate Research Assistant towards his PhD under the supervision of Dr. Swarup Bhunia (Professor, ECE, UF). Moshiur is a former Graduate Intern at Intel Corporation, and former graduate of Ahsanullah University of Science & Technology (AUST), Bangladesh.
He graduated with a PhD from the Department of Electrical and Computer Engineering (ECE) at University of Florida (UF), USA. He worked as a Graduate Research Assistant towards his PhD under the supervision of Dr. Swarup Bhunia (Professor, ECE, UF). Moshiur is a former Graduate Intern at Intel Corporation, and former graduate of Ahsanullah University of Science & Technology (AUST), Bangladesh.
Research Interests
Research Interests
Md Moshiur Rahman commenced his research focusing on the field of Hardware Security & Trust. He dealt with issues that are related with the security concern of integrated circuit (IC) supply chain in current business models. His research interest includes but not limited to the following specific areas:
Hardware Intellectual Property (IP) Trust and Verification
Computer-Aided-Design (CAD)
Electronic Design Automation (EDA)
To know about his research in the field of obfuscation in more details, click here.
TECHNICAL SKILLS
TECHNICAL SKILLS
Hardware Design & Verification
Hardware Design & Verification
IP Design
Constrained Logic Synthesis
Static Timing Analysis
Formal Equivalence Checking
Power Estimation using BE Collaterals
IP Integration to SoC
Functional Simulation (IP and SoC level)
Hands on Std. Cell Library (3nm, 7nm, 16nm, 45nm, 90nm, 250nm)
Synopsys
Synopsys
PrimePower
Design Compiler (DC)
Verilog Compiler & Simulator (VCS)
Prime Time (PT)
Formality
Cadence
Cadence
Genus
Incisive
Xcelium
JasperGold
Virtuoso
Ansys
Ansys
Power Artist
Xilinx
Xilinx
ISE Design Suite
Vivado
Altera (Intel)
Altera (Intel)
Quartus Prime
Mentor Graphics
Mentor Graphics
Model Sim
PCB Design
PCB Design
EasyEDA
Spice Simulators
Spice Simulators
Orcad PSpice
HDL
HDL
Verilog
VHDL
SystemVerilog
Programming
Programming
C/C++
MATLAB
Scripting
Scripting
TCL
Perl
Python
Shell
Regression Framework Setup
Contacts
Contacts
Work Address:
Work Address:
1300 S MoPac Expy
Austin, TX - 78746
USA
Headquarters:
Headquarters:
2200 Mission College Blvd
Santa Clara, CA - 95054
USA
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