Research activities
Current research projects
NAND - Noise Against Noise Decoder
Date: Feb. 2016 – December 2019
The objective of the NAND project is to improve the performance of an iterative decoder by a "smart injection" of randomness inside the decoding process.
The NAND Project is a collaborative research project funded by the french ANR under grant n° ANR-15-CE25-0006-01. The project involves 7 funded partners and 2 foreigns collaborators. The project started the first of January 2016 and will finish in December 2019.
Partners: Lab-STICC/Université de Bretagne Sud (Lorient), ETIS - UMR 8051, Cergy-Pontoise, IMS - UMR 5218 Bordeaux, Lab-STICC - UMR 8265 (Brest), Turbo-Concept, Thales Communications&Security (TCS), Christ Winstead (Utah State University, USA), and Bane Vasic (University of Arizona, USA).
Past research projects
Date: March 2014 - February 2017
Partners: Laboratoire des Equipes de Traitement de l'Information et Systèmes (ETIS) - France, Universitatea Politehnica Timisoara (UPT) - Romania, Commissariat à l’Energie Atomique et aux Energies Alternatives (CEA-LETI) - France.
Summary: throughput and power consumption are key challenges for next-generation communication systems. High throughput is required to support the continuously increasing demand of traffic volume, while power consumption incorporates sustainability concerns and is a major constraint in mobile devices. Due to the erroneous nature of communication channels, error correcting codes are essential to any communication system, no matter the way the information is transported, for instance using a point-to-point, multicast, or broadcast technology, a wired or wireless link, and a terrestrial, satellite-based or hybrid infrastructure. However, these error-correction mechanisms require intensive computing tasks that turn into a critical bottleneck both in terms of throughput and power consumption. The DIAMOND project proposes to exploit the robustness of modern decoders to arithmetic inaccuracies, for improving their latency and power consumption. The project focuses on graph-based codes that are widely used in modern communication systems, as Low-Density Parity-Check (LDPC) and Turbo codes, and targets the design of message-passing iterative decoders using imprecise arithmetic units. We aim at harnessing the inaccuracies produced by imprecise arithmetic, or more generally imprecise computational units, while benefiting of their significant reductions in area, latency and power consumption. The DIAMOND project will first provide the scientific foundation for both the theoretical analysis and practical design of imprecise iterative decoders. Then, imprecise computational units will be tailored to suit different requirements arising from the multi-objective optimization of the design with respect to energy consumption, latency and area. The proposed solutions will be assessed and validated through proof-of concept models and implementations. In the context of next-generation communication systems, DIAMOND presents a novel approach that tackles the increasingly stringent requirements for high data rates and low power consumption.
i-RISC - Innovative Reliable Chip Designs from Low-Powered Unreliable Components
Date: Feb. 2013 - Jan. 2016
i-RISC is a FET-OPEN project funded by the European Commission under the Seventh Framework Programme (Grant Agreement number 309129)
Partners:
1. CEA - Grenoble, France.
2. ETIS, ENSEA, France.
3. Technische Universiteit Delft, Netherlands
4. Universitatea Politehnica Timisoara, Romania
5. University College Cork, National University of Ireland, Ireland
6. University of Nis, Faculty of Electronic Engineering, Serbia
Context and Objectives: The on-going miniaturization of data processing and storage devices and the low-energy consumption imperative can only be sustained through low-powered components. However, lower supply voltages combined with the intrinsic device variations introduced by emerging nanoelectronic device fabrication process make them inherently unreliable. As a consequence, the nanoscale integration of reliable chips built out of unreliable components emerged as one of the most critical challenges for the next-generation electronic circuit design. To make such nanoscale integration economically viable, new solutions for efficient fault-tolerant data processing and storage must be investigated.
The i-RISC project targets a foundational breakthrough towards reliable, fault-tolerant chip design from unreliable components, which is a crucial issue for the computing technology long-term development. The research novelty emerges from the synergistic utilization of (1) information theory and coding techniques, traditionally utilized to improve the communication systems reliability and (2) circuit and system theory and design techniques, in order to create reliable/ predictable hardware. The aim is to enable the development of innovative fault-tolerant solutions at both circuit- and system-level that are fundamentally rooted in mathematical models, algorithms, and techniques from information and coding theory.
Proposed Approach - Error correcting codes utilization proved to be a fundamental cornerstone of information theory, providing an efficient solution to the problem of reliable communication over unreliable channels. The i-RISC project is aimed at shifting the error correction paradigm from communication to computing systems. The central i-RISC target is to acquire error-free computing with error-prone components. i-RISC proposes to tackle this problem by detouring error correcting codes from their traditional use, such that they provide efficient protection against circuit-induced errors. To make such an approach viable, both fundamental and exploratory research must be conducted at different circuit or system levels.