[J6] F. Cochachin, K. Le et al., "Analysis and design of the Noise-Against-Noise Min-Sum Decoders", IEEE Transactions on Circuits and Systems I: Regular Papers (in preparation).

[J5] Hangxuan Cui, Fakhreddine Ghaffari, Khoa Le, David Declercq, Jun Lin and Zhongfeng Wang, “Design of High-Performance and Area-Efficient Decoder for 5G LDPC Codes”, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 2, pp. 879 - 891, Feb. 2021 (IEEExplore)

[J4] K. Le, F. Ghaffari, L. Kessal, D. Declercq, E. Boutillon, C. Winstead and B. Vasíc, "A Probabilistic Parallel Bit-Flipping Decoder for Low-Density Parity-Check Codes", IEEE Transactions on Circuits and Systems I: Regular Papers, Jan. 2018 (IEEExplore link).

[J3] K. Le, D. Declercq, F. Ghaffari, L. Kessal, O. Boncalo and V. Savin, "Variable-Node-Shift based Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 65, no. 7, July. 2018. (IEEExplore link)

[J2] T. T. Nguyen-Ly, V. Savin, K. Le, D. Declercq, F. Ghaffari, and O. Boncalo, "Analysis and Design of Cost-effective, High-Throughput LDPC Decoders", IEEE Transactions on Very Large Scale Integration (VLSI) systems, vol. 26, no. 3, pp. 508-521, March. 2018. (IEEExplore link)

[J1] K. Le, F. Ghaffari, D. Declercq and B. Vasíc, "Efficient Hardware Implementation of Probabilistic Gradient Descent Bit-Flipping", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 64, no. 4, pp. 906 - 917, April 2017. (IEEExplore link)

[C20] A. Lorences-Riesgo; D. Bendimerad; Khoa Le Trung; I. F. de Jauregui Ruiz; Y. Zhao; M. Sales-Llopis; S. Kamel; K. Huang; C. S. Martins, D. Le Gac, S. Mumtaz, S. Dris, Y. Frignac, G. Charlet, "PCS-16QAM vs QPSK: What is the best choice for Next-Generation Long-Haul 400G?", 2021 European Conference on Optical Communication (ECOC), Bordeaux, France, 13-16 Sept. 2021 (IEEExplore)

[C19] Duc-Phuc Nguyen, Khoa Le Trung, Fakhreddine Ghaffari and David Declercq, "Reliability Enhancement for Multi-level Cell NAND Flash Memory Using Error Asymmetry", The 25th Asia-Pacific Conference on Communications (APCC), November, 2019, Hochiminh City, Vietnam.

[C18] Hangxuan Cui, Khoa Le Trung, Fakhreddine Ghaffari, David Declercq, Jun Lin and Zhongfeng Wang, "An Enhanced Offset Min-Sum decoder for 5G LDPC Codes", The 25th Asia-Pacific Conference on Communications (APCC), November, 2019, Hochiminh City, Vietnam.

[C17] Huangxuan Cui, Khoa Le Trung, Fakhreddine Ghaffari, David Declercq, Jun Lin and Zhongfeng Wang, "A Decomposition Mapping based Quantized Belief Propagation Decoding for 5G LDPC Codes", 2019 19th International Symposium on Communications and Information Technologies (ISCIT), September, 2019, Hochiminh City, Vietnam.

[C16] Duc-Phuc Nguyen, Khoa Le Trung, Fakhreddine Ghaffari and David Declercq, "Performance Enhancement of Polar Codes in Multi-level Cell NAND Flash Memories using Systematic Encoding", 2019 19th International Symposium on Communications and Information Technologies (ISCIT), September, 2019, Hochiminh City, Vietnam.

[C15] F. Ghaffari, K. Le, D. P. Nguyen and D. Declercq, "An Optimized Check-Node Architecture for 5G New Radio LDPC Decoders", The 62st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Dallas, TX, USA, 2019.

[C14] F. Ghaffari, K. Le and D. Declercq, "The Probabilistic Finite Alphabet Iterative Decoder for Low-Density Parity-Check Codes", The 17th IEEE International NEWCAS Conference, Munich, Germany, June 23-26, 2019 (accepted).

[C13] K. Le, F. Ghaffari and D. Declercq, "An Adaptation of Min-Sum Decoder for 5G Low-Density Parity-Check Codes", 2019 IEEE International Symposium on Circuits and Systems (ISCAS), Sapporo, Japan, May 2019 (IEEExplore), (Poster).

[C12] K. Le, F. Ghaffari and D. Declercq, "On the use of Probabilistic Parallel Bit-Flipping decoder for the storage systems", The 61st IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), Windsor, ON, Canada, August 5th-8th, 2018. (IEEExplore)

[C11] K. Le and F. Ghaffari, “On the Use of Hard-Decision LDPC Decoders on MLC NAND Flash Memory”, The International Multi-Conference on Systems, Signals and Devices 2018, Hammamet, Tunisia, March. 2018. (IEEExplore)

[C10] K. Le, F. Ghaffari, D. Declercq, L. Kessal, O. Boncalo and V. Savin, “Lightweight Hardware Architecture for Probabilistic Gradient Descent Bit Flipping on QC-LDPC Codes”, 2018 IEEE International Symposium on Circuits and Systems (ISCAS), Florence, Italy, May 2018. (IEEExplore)

[C9] F. Ghaffari, B. Unal, A. Akoglu, K. Le, D. Declercq and B. Vasíc, “Efficient FPGA Implementation of Probabilistic Gallager B LDPC Decoder”, The 24th Edition of IEEE International Conference on Electronic Circuits and Systems (ICECS), Batumi, Georgia, Dec. 2017. (IEEExplore)

[C8] K. Le, F. Ghaffari, D. Declercq, B. Vasíc and C. Winstead, “A Novel High-Throughput, Low- Complexity Bit-Flipping Decoder for LDPC Codes”, The 2017 IEEE International Conference on Advanced Technologies for Communications (ATC), Quynhon, Vietnam, Oct. 2017. (IEEExplore),(Slides)

[C7] K. Le, F. Ghaffari, D. Declercq and B. Vasíc, “Hardware Optimization of the Perturbation for Probabilistic Gradient Descent Bit Flipping Decoders”, 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Baltimore, M.D, USA, May 2017 (Honorable mentioned best student paper). (IEEExplore)

[C6] T. T. Nguyen-Ly, K. Le, V. Savin, D. Declercq, F. Ghaffari and O. Boncalo, “Non-surjective finite alphabet iterative decoders”, 2016 IEEE International Conference on Communications (ICC), KualaLumpur, Malaysia, May 2016. (IEEExplore)

[C5] B. Vasíc, P. Ivanis, D. Declercq and K. Le, “Approaching Maximum Likelihood Performance of LDPC Codes by Stochastic Resonance in Noisy Iterative Decoders”, Information Theory and Applications Workshop (ITA 2016), San Diego, CA, Feb. 2016. (IEEExplore)

[C4] T. T. Nguyen-Ly, K. Le, F. Ghaffari, A. Amaricai, O. Boncalo, V. Savin and D. Declercq, “FPGA design of high throughput LDPC decoder based on imprecise Offset Min-Sum decoding”, 2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), pp. 1 -4, Grenoble, France, June 2015. (IEEExplore)

[C3] K. Le, D. Declercq, F. Ghaffari, C. Spagnol, E. Popovici, P. Ivanis and B. Vasíc, “Efficient realization of probabilistic gradient descent bit flipping decoders”, 2015 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1494-1497, Lisbon, Portugal, May 2015. (IEEExplore)

[C2] T. Hoang and K. Le, “Design an optimized CPU architecture for pacemaker applications”, Mega-Conference on Biomedical engineering, Springer and International University - VNU, Hochiminh, Vietnam, Jan. 2012. (Springer)

[C1] K. Le and T. Hoang, “Power gating technique in pacemaker design on FPGA”, The 2012 IEEE International Conference on Advanced Technologies for Communications (ATC), Hanoi, Vietnam, Oct. 2012. (IEEExplore)

[S1] F. Ghaffari, K. Le, D. Declercq, C. Spagnol, E. Popovici, P. Ivanis and B. Vasíc, “Efficient realization of probabilistic gradient descent bit flipping decoders”, GDR ISIS meeting event, Paris, June 2016.

[W1] K. Le, F. Ghaffari and D. Declercq, “Efficient realization of probabilistic gradient descent bit flipping decoders”, 2nd i-RISC Workshop: When Boole Meets Shannon, Cork, Ireland, September 2015.

[P1] K. Le, D. Declercq, F. Ghaffari, C. Spagnol, E. Popovici, P. Ivanis and B. Vasíc, “Efficient realization of probabilistic gradient descent bit flipping decoders”, 2015 European School of Information Theory (ESIT), 20 - 24, April, Zandvoort, Netherlands.