1.  J. Debnath, MEH Sikder, and S. Singha, "Comparative Analysis of Gate-Oxide Engineering in Charge Plasma Nanowire Transistor."

In this study, the effects of two distinct gate oxide formation techniques were compared to the conventional technique. The charge plasma technique was applied to create the N+-I-N+ doping profile, which is induced by the work-function difference between metal electrodes on a low-doped substrate. The effects of stacking a high-κ gate oxide with a low-κ gate oxide beneath the gate and segmenting the gate oxide with a high-κ oxide at the source side and low-κ oxide at the drain side have been analyzed with the short channel effects (SCEs) parameters and radio-frequency (RF)/analog figure of merits. The HGO-CPNWT demonstrates enhanced performances in terms of Ion/Ioff of 1.66 × 108, subthreshold slope (SS) of 65.74 mV/decade, drain-induced barrier lowering (DIBL) of 47.857 mV/V, peak transconductance (gm) of 3.43 × 10−5 S/μm, and peak cut-off frequency (ft) of 114 GHz. The simulation employs a comprehensive quantum transport model, and the comparative impacts of adjusting channel length (Lg), nanowire radius (r), and gate oxide thickness (Tox) are studied.