Welcome to ICSL
Intelligent Circuits & Systems Laboratory
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About ICSL
The Intelligent Circuits & Systems Laboratory (ICSL) at Kangwon National University specializes in high-performance mixed-signal integrated circuit design, focusing on ultra-low jitter Frequency Synthesizers (PLL) for 5G/6G and WiFi-6, and high-efficiency Power Management ICs. We also develop robust Clock and Data Recovery (CDR) solutions for high-speed serial links and wireline communication.
Recent Notices
[Jun. 2026] Young-Ryul Yun, Seung-Jin Yeo, Jae-hong Ko, Muhammad Abrar Akram, and In-Chul Hwang
Paper accepted in IEEE Transactions on Circuits and Systems II (TCAS-II).
"A Low-Power Semi-Digital Spectrum-Balancing Adaptive Equalizer for 8Gb/s Serial Links"
[May 2026] Young-Ryul Yun, Min-Jeong Son, Do-Yeon Jeon, Ji-Seul Yoon, Muhammad Abrar Akram, and In-Chul Hwang
Presented at oral session of IEEE International Symposium on Circuits and Systems (ISCAS) 2026.
"A1.2−3.4 Gb/s Low-Power Multiphase CDR with Glitch-Free Bang-Bang Phase Detector"
[Mar. 2026] Jonghoon Park, Dongyong Choi, Jungmin Kwon, Kabseok Ko, Kuduck Kwon, In-Chul Hwang and Seungyoung Park
Paper accepted in IEIE Journal of Semiconductor Technology and Science (JSTS).
"Batch Bayesian Optimization for Minimizing IPN in RF PLLs"
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