Welcome to ICSL
Intelligent Circuits & Systems Laboratory
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About ICSL
The Intelligent Circuits & Systems Laboratory (ICSL) at Kangwon National University specializes in high-performance mixed-signal integrated circuit design, focusing on ultra-low jitter Frequency Synthesizers (PLL) for 5G/6G and WiFi-6, and high-efficiency Power Management ICs. We also develop robust Clock and Data Recovery (CDR) solutions for high-speed serial links and wireline communication.
Recent Notices
[2026.03] Jonghoon Park, Dongyong Choi, Jungmin Kwon, Kabseok Ko, Kuduck Kwon, In-Chul Hwang and Seungyoung Park
IEIE 주관 Journal of Semiconductor Technology and Science (JSTS)에 Accept 되었습니다.
"Batch Bayesian Optimization for Minimizing IPN in RF PLLs"
[2026.01] Young-Ryul Yun, Min-Jeong Son (Alumni), Do-Yeon Jeon, Ji-Seul Yoon, Muhammad Abrar Akram (Alumni), and In-Chul Hwang
IEEE 주관 IEEE International Symposium on Circuits and Systems (ISCAS) 2026에 Accept 되었음.
"A1.2−3.4 Gb/s Low-Power Multiphase CDR with Glitch-Free Bang-Bang Phase Detector"
[2026.01] Ibrar Ali Wahla, Jongwoon Lee, Young-Ryul Yun, Muhammad Abrar Akram and In-Chul Hwang
IEEE 주관 IEEE Open Journal of Power Electronics에 Accept 되었음.
"A Fast-Transient Digital LDO With Asynchronous Coarse and Dual-Mode Fine Regulation Loops"
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