SRAM Design

The data-dependent power controlling circuit is controlled by the WLA and WLB signals, which internally cut off the M9 and M10 transistors from the bitlines during read operation and resolve the half select issue.

In the power controlling circuit, one side of the inverter is cutoff from the bitlines, which inherently reduced the write power of the proposed D2LP10T cell.

The access transistor of the proposed cell is free from the bitline control, which reduces the read power at the lower supply voltage.

The stacking combination is present in the pull-up and pull-down path, which drastically reduces the leakage power also in the subthreshold region.

The trade-off between write/read operation is resolved by the read-decoupled approach and enhances the RSNM value inherently without any power penalty.

The data dependent circuit is used to reduced the dynamic power and enhance the write ability of the circuit.

The area penalty is reduced by removing the access transistor from the proposed cell.

Extra NMOS sleep transistor is used to form virtual ground (V-GND) node which reduces the leakage power.

Read decoupling technique is used to resolve the problem of read/write trade-off and to improve the RSNM.

The data dependent power supply is powered by bit lines (BL and BLB), which drastically reduces the dynamic power.

Stacked combination integrated with pull-down path of inverter pair, which supports to enhance write stability and reduce the leakage power of the cell.

Additional NMOS transistor connected in write access path select the column-wise line and resolve the issue regarding write half select.

Read decoupling technique is used to resolve the problem of read/write trade-off and to improve the RSNM.