RESEARCH

1. DAC-ADC-DSP-based PAM-4/8 wireline transceivers for high-performance computing systems and datacenters

Ultra high-speed low-power inter-chip data movement

• Data converter design for >112Gb/s serial link (SerDes) for wireline communications

• High-speed mid-resolution time-interleaved analog-digital converter (ADC) design

• >112Gb/s/lane PAM-4/8 ADC- and DSP-based receiver

• High-level SerDes modeling and simulation

• Wired communication protocol for low-power dataflow management

2. Advanced modulation and energy-efficient circuit design for ultra-high-speed wireline serial links

Squeeze more bits per Hertz (bits/Hz) for better bandwidth efficiency, less power, and higher data rate

• Orthogonal frequency-division multiplexing (OFDM) for bandwidth-efficient >200Gb/s/lane chip-to-chip communications

• High-performance digital-to-analog and analog-to-digital converters design for the analog-digital interface

• OFDM-specific ADC/DAC design with non-uniform quantization threshold

• Energy-efficient channel estimation and clock recovery algorithm for wireline OFDM

• Crosstalk reduction/cancellation through multi-input multi-output (MIMO) transceiver for dense chip-to-chip interconnects

3. Real-time ADC-DSP-based ASIC prototyping with programmable RFSoC

Real-time hardware emulation of DAC-ADC-DSP-based transceivers

• Rapid prototyping of mixed-signal circuits in real-time before tapeout

• Digital signal processor (DSP) design in Field Programmable Gate Array (FPGA)

• Pre-tapeout functional and performance evaluation of high-speed DSP-DAC-based transmitter and ADC-DSP-based receiver designs in hardware (>10000x evaluation speed boost over computer simulation)

• Quick demonstration of modulation scheme and signal processing ideas for ADC-DSP-based mixed-signal systems

4. Signal processing, circuit, and system design for high-performance multi-chip system

Maximizing system-level performance of wireline transceivers for chip-to-chip communications

• Adaptive transceiver performance optimization algorithm

• Encoding/decoding scheme for pin-efficient balanced multi-bit multi-wire signaling

• Area- and power-efficient circuit design for crosstalk cancellation in dense interconnects