PUBLICATIONS

*: Equal contribusion

2025

• [J23] J. Lee, P.-A. Francese, M. Braendli, T. Morf, M. Kossel, S. Jang, Y. Choi, D. Kim, T. Jang, and G. Kim, "A 112 Gb/s discrete multitone wireline receiver datapath with time-interleaved time-based ADC in 5nm FinFET," IEEE Journal of Solid-State Circuits (JSSC), 2025. (accepted for publication)

• [J22] H. Choi, H.-I. Song, H. Won, J. Yoo, W. Kwon, H. Jin, K. Kwon, C. Lee, G. Kim, J. Eu, S. Park, H.-M. Bae, "An 86.71875GHz RF Transceiver for 57.8125Gb/s Plastic Waveguide Links With a CDR-Assisted Carrier Synchronization Technique in 28nm CMOS," IEEE Journal of Solid-State Circuits (JSSC), Mar. 2025.

• [J21] J. Lee*, S. Jang*, Y. Choi, D. Kim, M. Braendli, T. Morf, M. Kossel, P.-A. Francese, G. Kim, "A 2-lane DAC/ADC-based 2x2 MIMO PAM-4 MMSE-DFE wireline transceiver with FEXT cancellation on RFSoC platform," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 33, no. 6, pp. 1570-1581, Mar. 2025. (* both authors contributed equally to this work)

2024

• [J20] S. Jang, J. Lee, Y. Choi, D. Kim, and G. Kim, "Recent advances in ultra-high-speed wireline receivers with ADC-DSP-based equalizers," IEEE Open Journal of the Solid-State Circuits Society (OJ-SSCS), vol. 4, pp. 290-304, Nov. 2024.

• [J19] H. Song, K. Kim, G. Kim, B. Kim, "A fast design optimization of on-chip equalizing links using particle swarm optimization," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol, 33, no. 1, pp. 1-9, Jan. 2025.

• [J18] J. Lee, D.-G. Choi, G. Kim, M. Song, J.-H. Yoon, "BEE-SLAM: A 65nm 17.96 TOPS/W location-sharing-based multi-agent neuromorphic SLAM accelerator for swarm robotics," IEEE Journal of Solid-State Circuits (JSSC), vol. 60, no. 3, pp. 963-976, Mar. 2025.

• [J17] W.-J. Choi, M. Lee, J. Choi, J. Cho, G. Kim, B. Kim, "An on-chip low-cost averaging digital sampling scope for 80GS/s measurement of wireline pulse responses," IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol. 33, no. 5, pp. 1432-1436, May. 2025.

• [J16] J. Lee*, S. Jang*, D. Kim, Y. Choi, J.-H. Yoon, M. Braendli, T. Morf, M. Kossel, P.-A. Francese, G. Kim, "A discrete multitone wireline transceiver datapath with on-chip sign-sign LMS adaptation and loading profile optimization on RFSoC," IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 71, no. 12, pp. 4889-4893, Dec. 2024. (* both authors contributed equally to this work)

• [J15] D. Kim*, Y. Choi*, J. Lee, S. Jang, S. Song, M. Braendli, T. Morf, M. Kossel, P.-A. Francese, G. Kim, "A loop-break decision feedback equalizer for DAC/ADC-DSP-based wireline transceivers," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 71, no. 11, pp. 5115-5128, Nov. 2024. (* both authors contributed equally to this work)

• [J14] H. Kim, J.-H. Kim, M. Jeong, D. Lee, J. Kim, M. Lee, G. Kim, J. Kim, J.-S. Lee, J. Lee "Bioelectronic sutures with electrochemical pH-sensing for long-term monitoring of the wound healing progress," Advanced Functional Materials, vol. 34, no. 40, July. 2024.

• [J13] J. Lee, S. Jang, M. Braendli, T. Morf, M. Kossel, P.-A. Francese, G. Kim, "A 2-lane discrete multitone wireline receiver datapath with far-end crosstalk cancellation on RFSoC platform," IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 71, no. 11, pp. 4738-4742, June. 2024. (accepted for publication)

• [J12] W. Kwon, H. Won, T. Kim, S. Jeon, S.-W. Kwon, H.-I. Song, H. Choi, B. Kim, H. Jin, J.-G. Jo, W. Han, T.-Y. Kim, G. Kim, J. Eu, J. Park, H.-M. Bae, "A 26Gb/s framed-pulse width modulation transceiver for extended reach optical links," IEEE Journal of Solid-State Circuits (JSSC), vol. 59, no. 8, pp. 2506-2517, Feb. 2024.

• [J11] J. Lee, S. Jang, Y. Choi, D. Kim, S. Yonar, M. Braendli, A. Ruffino, T. Morf, M. Kossel, P.-A. Francese, G. Kim, "A DAC/ADC-based wireline transceiver datapath functional verification on RFSoC platform," IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 71, no. 7, pp. 3318-3322, Feb. 2024.

• [J10] M. Lee, J. Cho, J. Choi, W. Choi, J. Lee, I. Jang, C. Moon, G. Kim, B. Kim, "Compact single-ended transceivers demonstrating flexible generation of 1/N-rate receiver front-ends for short-reach links," IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 71, no. 1, pp. 373-382, Jan. 2024.

2023

• [J9] A.-S. Yonar, P.-A. Francese, M. Braendli, M. Kossel, M. Prathapan, T. Morf, A. Ruffino, G. Kim, T. Jang, "An 8b 1.0-to-1.25GS/s time-based ADC with bipolar VTC and sense amplifier latch interpolated gated ring oscillator TDC," IEEE Solid-State Circuits Letters (SSCL), vol. 6, pp. 193-196, Jul. 2023.

• [J8] G. Kim, "Far-end crosstalk cancellation with MIMO OFDM for >200 Gb/s ADC-based serial links," IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), Jan. 2023.

2022

• [J7] G. Kim, "Design space exploration of single-lane OFDM-based serial links for high-speed wireline communications," IEEE Open Journal of Circuits and Systems (OJCAS), vol. 3, pp. 134-146, Jul. 2022.

2020

• [J6] G. Kim, L. Kull, D. Luu, M. Braendli, C. Menolfi, P.-A. Francese, H. Yueksel, C. Aprile, T. Morf, M. Kossel, A. Cevrero, I. Ozkaya, A. Burg, T. Toifl and Y. Leblebici, "A 161mW 56Gb/s ADC-based discrete multitone wireline receiver data-path in 14nm FinFET," IEEE Journal of Solid-State Circuits (JSSC), vol. 55, no. 1, pp. 38-48, Jan. 2020.

Before 2019

• [J5] G. Kim, C. Cao, K. Gharibdoust, A. Tajalli, and Y. Leblebici, "A time-division multiplexing signaling scheme for inter-symbol/channel interference reduction in low-power multi-drop memory links," IEEE Transactions on Circuits and Systems II: Regular papers (TCAS-II), vol. 64, no. 12, pp. 1387-1391, December 2017.

• [J4] G. Kim, T. Barailler, C. Cao, K. Gharibdoust and Y. Leblebici, "Design and modeling of serial data transceiver architecture by employing multi-tone single-sideband signaling scheme," IEEE Transactions on Circuits and Systems I: Regular papers (TCAS-I), vol. 64, no. 12, pp. 3192-3201, December 2017.

• [J3] G. Kim, K. Gharibdoust, A. Tajalli and Y. Leblebici, "A digital spectrum shaping signaling serial-data transceiver with crosstalk and ISI reduction property in multi-drop interfaces," IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II), vol. 63, no. 12, pp. 1126-1130, December 2016.

• [J2] X. Tang, G. Kim, P.-E. Gaillardon and G. De Micheli, "A study on the programming structures for RRAM-based FPGA architectures," IEEE Transactions on Circuits and Systems I: Regular papers (TCAS-I), vol. 63, no. 10, pp. 503-516, April 2016.

• [J1] P.-E. Gaillardon, X. Tang, G. Kim and G. De Micheli, "A novel FPGA architecture based on ultra-fine grain reconfigurable logic cells," IEEE Transactions on Very Large Scale Integration (TVLSI) Systems, vol. 23, no. 10, pp. 2187-2197, October 2015.

2025

• [C24] S. Jang*, J. Lee*, M. Kossel, M. Brandli, T. Morf, P.-A. Francese, G. Kim, "A 144mW 76Gb/s DAC-Based Discrete Multitone Wireline Transmitter in 5nm FinFET," 2025 European Solid-State Electronics Research Conference (ESSERC 2025), Munich, Germany, September 8-11, 2025. (* both authors contributed equally to this work)

• [C23] D. Kim, K. Gharibdoust, A. Tajalli, K. Lee, G. Kim, "A Spectral-Efficient Low-Power NRZ/PAM-4 Dual-Mode Wireline Transmitter for Multidrop Interfaces," 2025 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED 2025), Iceland, Aug. 6-8, 2025.

• [C22] J. Lee, P.-A. Francese, M. Brandli, T. Morf, M. Kossel, S. Jang, G. Kim, "A 353mW 112Gb/s Discrete Multitone Wireline Receiver Datapath With Time-Based ADC in 5nm FinFET," 2025 International Solid-State Circuits Conference (ISSCC 2025), San-Francisco, California, USA, February 16-20, 2025.

2024

• [C21] S. Jang, J. Lee, Y. Choi, D. Kim, G. Kim, "A Discrete Multitone Wireline Transceiver With Clipping Ratio Optimization For ADC-Based High-Speed Serial Links," 21st International SoC Design Conference (ISOCC 2024), Sapporo, Japan, August 19-22, 2024.

• [C20] J. Lee, S. Jang, D. Kim, Y. Choi, S. Song, G. Kim, "A Discrete Multitone Wireline Transceiver Using Optimal Loading Over Reflective Channel For ADC-Based High-Speed Serial Links," 21st International SoC Design Conference (ISOCC 2024), Sapporo, Japan, August 19-22, 2024.

• [C19] S. Lee, T. Seol, G. Kim, M. Song, G. Kim, J.-H. Yoon,  A.-K. George, J. Lee, "A 97dB-PSRR 178.4dB-FOMDR calibration-free VCOΔΣ ADC using a PVT-insensitive frequency locked differential regulation scheme for multi-channel ExG acquisition," 2024 IEEE Symposium on VLSI Technology and Circuits (VLSI 2024), Jun. 2024.

• [C18] S. Jang, J. Lee, Y. Choi, D. Kim, G. Kim, "DMT 3L4W: a 3-lane 4-wire signaling with discrete multitone modulation for high-speed wireline chip-to-chip interconnects," 2024 International Symposium on Circuits and Systems (ISCAS 2024), Singapore, May 19-22, 2024.

• [C17] J. Lee, S. Jang, Y. Choi, D. Kim, M. Braendli, M. Kossel, A. Ruffino, T. Morf, P.-A. Francese, G. Kim, "A 4x4 MIMO discrete multitone wireline transceiver with far-end crosstalk cancellation for ADC-based high-speed serial links," 2024 International Symposium on Circuits and Systems (ISCAS 2024), Singapore, May 19-22, 2024.

• [C16] J. Lee, D.-G. Choi, M. Song, G. Kim, J.-H. Yoon, "BEE-SLAM: a 65nm 17.96 TOPS/W 97.55%-sparse-activity hybrid mixed-signal/digital multi-agent neuromorphic SLAM accelerator for swarm robotics," 2024 Custom Integrated Circuits Conference (CICC), Denver, Apr., 2024.

• [C15] S. Jang, J. Lee, G. Kim, "A study on the effects of power loading profile in discrete multitone wireline serial-data transceiver with fixed-point DSP-SerDes simulator," 2024 International Conference on Electronics, Information, and Communication (ICEIC 2024), Taipei, Taiwan, Jan. 28-31, 2024.

• [C14] Y. Choi, S. Jang, G. Kim, "Area optimization of the feed-forward equalizer for ADC-based high-speed wireline receiver using channel characteristics," 2024 International Conference on Electronics, Information, and Communication (ICEIC 2024), Taipei, Taiwan, Jan. 28-31, 2024.

2023

• [C13] H. Choi, H.-I. Song, H. Won, J. Woo, W. Kwon, H. Jin, K. Kwon, C. Lee, G. Kim, J. Eu, S. Park, H.-M. Bae, "An 86.71875GHz RF transceiver for 57.8125Gb/s waveguide links with a CDR-assisted carrier synchronization loop in 28nm," 2023 European Solid-State Circuits Conference (ESSCIRC 2023), Lisbon, Portugal, September 11-14, 2023.

• [C12] G. Kim, S. Lee, T. Seol, S. Baik, Y. Shin, G. Kim, J-H. Yoon, A-K. George, J. Lee, "A 1V-supply 1.85Vpp-input-range 1kHz-BW 181.9dB-FOMDR 179.4dB-FoMSNDR 2nd-order noise-shaping SAR-ADC with enhanced input impedance in 0.18um CMOS," 2023 International Solid-State Circuits Conference (ISSCC 2023), San-Francisco, California, USA, February 19-23, 2023.

2022

• [C11] J. Park, J. Lee, G. Kim, and H.-M. Bae, "Bin-specific quantization in spectral-domain convolutional neural network accelerators," IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2022), Incheon, South Korea, June 13-15, 2022.

2021

• [C10] J. Lee*, G. Kim*, J. Park and H.-M. Bae, "Link bit-error rate requirement analysis for deep neural network accelerators," IEEE International Symposium on Circuits and Systems (ISCAS 2021), Daegu, South Korea, May 22-28, 2021. (*Both authors contributed equally to this work)

2019

• [C9] G. Kim, L. Kull, D. Luu, M. Braendli, C. Menolfi, P.-A. Francese, H. Yueksel, C. Aprile, T. Morf, M. Kossel, A. Cevrero, I. Ozkaya, H. Bae, A. Burg, T. Toifl and Y. Leblebici, "A 4.8pJ/b 56Gb/s ADC-based PAM-4 wireline receiver data-path with cyclic prefix in 14nm FinFET," 2019 Asian Solid-State Circuits Conference (ASSCC 2019), Macao, China, November 4-6, 2019.

• [C8] G. Kim, Woohyun Kwon, Thomas Toifl, Yusuf Leblebici, Hyeon-Min Bae, "Design considerations and performance trade-offs for 56Gb/s discrete multi-tone electrical link," 62nd IEEE International Midwest Symposium on Circuits and Systems (MWSCAS 2019), Dallas, TX, USA, August 4-7, 2019.

• [C7] G. Kim, L. Kull, D. Luu, M. Braendli, C. Menolfi, P.-A. Francese, H. Yueksel, C. Aprile, T. Morf, M. Kossel, A. Cevrero, I. Ozkaya, A. Burg, T. Toifl and Y. Leblebici, "A 161mW 56Gb/s ADC-based discrete multitone wireline receiver data-path in 14nm FinFET," 2019 International Solid-State Circuits Conference (ISSCC 2019), San-Francisco, California, USA, February 17-21, 2019.

Before 2019

• [C6] G. Kim, L. Kull, D. Luu, M. Braendli, C. Menolfi, P.-A. Francese, H. Yueksel, C. Aprile, T. Morf, M. Kossel, A. Cevrero, I. Ozkaya, T. Toifl and Y. Leblebici, "Parallel implementation technique of digital equalizer for ultra-high-speed wireline receiver," IEEE International Symposium on Circuits and Systems (ISCAS 2018), Florence, Italy, May 27-30, 2018.

• [C5] G. Kim, K. Gharibdoust, Y. Leblebici, "Analysis, Optimization, and Modeling of Analog Multi-Tone Serial Data Transceivers," IEEE 13th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME 2017), Taormina, Italy, 2017.

• [C4] G. Kim, Y. Leblebici, "Architectural Modeling of a Multi-Tone/Single-Sideband Serial Link Transceiver for Lossy Wireline Data Links," IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2016), Jeju, South Korea, 2016.

• [C3] G. Kim, Y. Leblebici, "Architectural Modeling of a Single-Sideband Wireline Serial Data Transceiver for Multi-Drop I/O," IEEE 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME 2016), Lisbon, Portugal, 2016.

• [C2] G. Kim, R. Capoccia, Y. Leblebici, "Design Optimization of Polyphase Digital Down Converters for Extremely High Frequency Wireless Communications," IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC 2015), Daejeon, South Korea, 2015.

• [C1] P.-E. Gaillardon, X. Tang, G. Kim, G. De Micheli, "Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion," Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA 2015), Monterey, California, Feb., 2015.