Journal Information:- (IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 9, No. 12, 2018.

Abstract:- Reliability and fault tolerance of FPGA systems is a major concern nowadays. The continuous increase of the system’s complexity makes the reliability evaluation extremely difficult and costly. Redundancy techniques are widely used to increase the reliability of such systems. These techniques provide a large area & time overheads which cause more power consumption and delay, respectively. An experimental evaluation method is proposed to find critical nodes of the FPGA-based designs, named “hardness analysis technique” under the proposed RASP-FIT tool. After finding the critical nodes, the proposed redundant model is applied to those locations of the design and the code is modified. The modified code is functionally equivalent and is more hardened to the soft-errors. An experimental set-up is developed to verify and validate the criticality of these locations found by using hardness analysis. After applying redundancy to those locations, the reliability is evaluated concerning failure rate reduction. Experimental results on ISCAS’85 combinational benchmarks show that a min-max range of failure reduction (14%-85%) is achieved compared to the circuit without redundancy under the same faulty conditions, which improves reliability.

Keywords—Dependability; fault injection; fault tolerance; reliability; single event effects.

Journal Information:- (IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 9, No. 10, 2018.

Abstract:- Fault Injection (FI) is the most popular technique used in the evaluation of fault effects and the dependability of a design. Fault Simulation/Emulation (S/E) is involved in several applications such as test data generation, test set evaluation, circuit testability, fault detection & diagnosis, and many others. These applications require a faulty module of the original design for fault injection testing. Currently, Hardware Description Languages (HDL) are involved in improving methodologies related to the digital system testing for Field Programmable Gate Array (FPGA). Designers can perform advanced testing and fault S/E methods directly on HDL. To modify the HDL design, it is a very cumbersome and time-consuming task. Therefore, a fault injection tool (RASP-FIT) is developed and presented, which consists of a code-modifier, fault injection control unit and result analyser. However, in this paper, code modification techniques of RASP-FIT are explained for the Verilog code at different abstraction levels. By code-modification, it means that a faulty module of the original design is generated which includes different permanent and transient faults at every possible location. The RASP-FIT tool is an automatic and fast tool which does not require much user intervention. To validate these claims, various faulty modules for different benchmark designs are generated and presented.

Keywords—Code generator; Fault emulation; Fault injection; Fault simulation; Instrumentation; Parser.

Journal Information:- (IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 9, No. 8, 2018.

Abstract:- Triple Modular Redundancy (TMR) technique is one of the most well-known techniques for error masking and Single Event Effects (SEE) protection for FPGA designs. These FPGA designs are mostly expressed in hardware description languages, such as Verilog and VHDL. The TMR technique involves the triplication of the design module and adding the majority voter circuit for each output port. Building this triplication scheme is a non-trivial task and requires a lot of time and effort to alter the code of the design. In this paper, the RASP-TMR tool is developed and presented that has functionalities to take a synthesizable Verilog design file as an input, parse the design and triplicate it. The tool also generates a top-level module in which all three modules are instantiated and finally adds the proposed majority voter circuit. This tool, with its graphical user interface, is implemented in MATLAB. The tool is simple, fast and user-friendly. The tool generates the synthesizable design that facilitates the user to evaluate and verify the TMR design for FPGA-based systems. A simulation scenario is created using Xilinx ISE tools and an ISim simulator. Different fault models are examined during simulations such as bit-flip and stuck at 1/0. The results using various benchmark designs demonstrate that the tool produces synthesizable code and the proposed majority voter logic perfectly masks the error/failure.

Keywords—Fault injection; fault tolerance; reliability; single event effects; triple modular redundancy; Verilog HDL.

Journal Information:- (IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 10, No. 12, 2019

Abstract:- Fault injection tools are designed to serve various purposes, such as validate the design under test concerning reliability requirements, find sensitive/critical locations that require error mitigation, determine the expected circuit response in the existence of faults. Fault Simulation/Emulation (S/E) applications are involved in Field Programmable Gate Array (FPGA) based design’s verification and simulation at the Hardware Description Languages (HDL) code level. A tool is developed, named RASP- FIT, to perform code modification of FPGA designs, testing such designs, and finding the sensitive area of designs. This tool works on the FPGA designs written in Verilog HDL at various abstraction levels, gate, data-flow and behavioural levels. This paper presents a technical aspect and the user-guide for the proposed tool in detail, which includes the generation of the standalone application (an executable file of the tool for Windows operating system) and installation method.

Keywords—Code-modifier; fault injection; FPGA designs; fault injection tool; Verilog HDL.

Journal Information:- (IJACSA) International Journal of Advanced Computer Science and Applications, Volume 11 Issue 8, 2020.

Abstract:- Fault simulation is the critical approach for many applications such as fault detection & diagnostics, test set quality measurement, generation of test vectors, circuit testability, and many others along with the help of fault injection technique. The fault simulation approach is divided into many types. The most straightforward approach among them is a serial fault simulation. In the simulation process, the circuit under test is faulted, and a faulty copy is achieved by either using a simulator command technique or instrumentation technique. A fault simulator must examine the behaviour of specified target fault in design and classified as detected or undetected by the applied test patterns. To modify the original code is a very challenging and time-consuming task. Therefore, the RASP-FIT tool is developed, which alters the fault-free FPGA design, which is under investigation, at the Verilog HDL code level. It produces the copies of faulty design along with the top design file for several fault simulation methods. Using this tool, a serial fault simulation environment can easily be created with no much effort. In this work, a serial fault simulation method is verified and validated using the RASP-FIT tool for an ISCAS’85 benchmark design as an example.

Keywords—FPGA design; fault injection; fault simulation; RASP-FIT tool; Verilog HDL

Journal Information:- (IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 11, No. 4, 2020.

Abstract:- The FPGA has been involved in many safety and mission-critical applications in the last few decades. FPGA designs are also critical to errors and failures due to radiations. Fault-tolerant systems should be designed to overcome the effect of faults or failure during the operation of the systems. The primary objective of any fault tolerance technique is to produce a dependable system. Fault tolerance techniques add the capability to perform proper functioning in the presence of a fault. Fault-tolerant techniques can detect the faults and correct them, or mask the faults. The overview of the most standard techniques used for FPGA designs is described in the paper. Among them, it is found that the Triple Modular Redundancy (TMR) technique is the most straight forward in terms of implementation and easy to use. The proposed TMR code generator for implementing the FPGA design is also described. These FPGA designs are written in Verilog Hardware Description Language (HDL) at the different abstraction levels.

Keywords—FPGA designs; fault tolerance; TMR technique; Verilog HDL

Journal Information:- (IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 10, No. 1, 2019

Abstract:- An embedded system is a dedicated computer system in which hardware and software are combined to perform some specific tasks. Recent advancements in the Field Programmable Gate Array (FPGA) technology make it possible to implement the complete embedded system on a single FPGA chip. The fundamental component of an embedded system is a microprocessor. Soft-core processors are written in hardware description languages and functionally equivalent to an ordinary microprocessor. These soft-core processors are synthesized and implemented on the FPGA devices. In this paper, the OpenRISC 1200 processor is used, which is a 32-bit soft-core processor and written in the Verilog HDL. Xilinx ISE tools perform synthesis, design implementation and configure/program the FPGA. For verification and debugging purpose, a software toolchain from GNU is configured and installed. The software is written in C and Assembly languages. The communication between the host computer and the FPGA board is carried out through the serial RS- 232 port.

Keywords—FPGA Design; HDLs; Hw-Sw Co-design; Open-RISC 1200; Soft-core processors

Journal Information:- (IJACSA) International Journal of Advanced Computer Science and Applications, Vol. 10, No. 4, 2019

Abstract:- Soft-core processors and complex Field Programmable Gate Array (FPGA) designs are described as an algorithmic manner, i.e. behavioural abstraction level in Hardware Description Languages (HDL). Lower abstraction levels add complexity and delays in the design cycle as well as in the fault injection approach. Therefore, fault simulation/emulation techniques are demanded to develop an approach for testing of design and to evaluate dependability analysis of FPGA designs at this abstraction level. Broadly, the fault injection techniques for FPGA-based designs at the HDL code level are categorised into emulation and simulation-based techniques. This work is an extension of our previous methodologies developed for FPGA designs written at data-flow and gate abstraction levels under the proposed RASP-FIT tool. These methodologies include fault injection by code parsing of the SUT, test approach for finding the test vectors using dynamic and static compaction techniques, fault coverage, and compaction ratio directly at the code level of the design. In this paper, we described the proposed approaches briefly, and the enhancement of a Verilog code modifier for the behavioural designs is presented in detail.

Keywords— Behavioural designs; code parsing; fault injection; test approach; Verilog HDL

Journal Information:- Bahria University Journal of Information & Communication Technologies Vol. 11, Issue II, December 2018

Abstract:- Fault injection technique is the most popular technique for characterising the dependability parameter of Very Large Scale Integrated (VLSI) systems and designs. Due to technology scaling, Field Programmable Gate Array (FPGA) systems are also prone to error and failure; hence fault injection tools play a vital role to test and evaluating dependability parameters. These tools are categorised into two techniques; reconfiguration and instrumentation-based techniques for FPGA fault injection tools. The primary focus is put on instrumentation-based fault injection tools and techniques in this paper. In the instrumentation technique, a specific circuit is appended to the original design to carry out fault injection analysis. This paper presents the comparison between various fault injection tools based on methodology, fault models consideration, fault injection control unit and functions they perform.

Keywords— Dependability analysis, Instrumentation, Fault injection, FPGA, Reliability, Fault tolerance.

Journal Information:- International Journal of Computer Science and Information Security (IJCSIS), Vol. 15, No. 6, June 2017

Abstract:- In this paper, the use of different techniques of redundancy for FPGA-based circuits and systems are highlighted. With the growing use of FPGA-based designs in various applications nowadays, for example in aerospace, traffic signalling and biomedical, there is a need for a robust and fault-tolerant design in order to prevent systems from failure. For that purpose, various redundant techniques are used to implement the logic on FPGA. One of the most commonly used and the state of the art technique for FPGA systems is the Triple Modular Technique (TMR). The main demerit of this technique is larger area overhead; the larger area leads to more power consumption. Many techniques also have been proposed to optimize FPGA design. The well-known techniques are Duplicate With Comparison (DWC) and N-modularity. The main objective of this paper is to study, compare and test the various hardware redundant techniques used in the field of FPGA-based embedded systems. Furthermore, the experiment on the OR1200 ALU circuit validates the comparison between these techniques.

Keywords— TMR; fault-tolerant; redundancy technique; FPGA; DWC;

Journal Information:- QUAID-E-AWAM UNIVERSITY RESEARCH JOURNAL OF ENGINEERING, SCIENCE & TECHNOLOGY, VOLUME 15, No.1, JAN-JUN 2016

Abstract:- Nowadays, the Field Programmable Gate Array (FPGA) is one of the most widely used components in the field of embedded system designs. Owing to its diverse advantages, it is used in the development of the system on chip (SoC), Application Specified Integrated Circuits (ASICs), Reconfigurable ICs and Digital Signal Processors (DSPs). There are many vendors, which provide the FPGA with different capacities and functionalities. Xilinx Corporation is one of the major providers of FPGAs. The major families of Xilinx FPGA include Spartan, Virtex, Artix and Kintex. Each member of their family is different based on the capacity, features and capability to perform certain functions. In this paper, a technical survey about the Xilinx FPGA families is presented along with the technical analysis, which includes growth in capacity, clock rate, the suitability of an FPGA for a particular application. In the end, Open RISC-1200’s ALU circuit is implemented on the Spartan-3E family of FPGA and simulated using Xilinx ISE, to give an idea of the implementation of the circuit on FPGA.

Keywords— FPGA, Xilinx ISE, Look-up table, Spartan, Virtex.