September 2024 -- present
November 2023 -- Present.
August 2022 -- Onwards
March 2021-- August 2022
Developed a fault injection tool (named RASP-FIT tool) for FPGA-based designs.
Developed ATPG method with a hybrid compaction technique for combinational digital systems written in Verilog HDL.
Sensitive analysis for FPGA-based designs for reliability improvements by reducing Soft-Error Rate (SER).
Development of the RASP-TMR code generator for Triple Modular Redundancy (TMR) technique for FPGA-based design.
ASIC chip testing and verification of SoCs based on ColdFire v4 and v2 processors.
Development and designing of modules and test benches for simulation and verification using Xilinx ISE Tools, Mentor graphics Modelsim and Cadence tools.
Documentation (user guide and integration guide) for ColdFire Processor.
Courses Taught: Basic and Advanced Electronics, Digital Electronics, C/C++ Programming, Signals and Systems, Digital Signal Processing, Control System, Power Electronics, Microprocessor and Microcontroller, Fiber Optics Communication and FPGA-based System Designs.
Developed and managed Curriculum
Involved in research and development
Conducted various workshops on different research topics
Supervised final year projects & theses
Courses Taught: C/C++ Programming, Measurement and Instrumentation, Control System.
Involved in research and development
Conducted various workshops on different research topics
Familiarization with different sensors such as temperature sensors, load sensors, proximity sensors etc.
Technical demonstrations with all departments