Conference Details:- 2018 IEEE 16th Intl Conf on Dependable, Autonomic and Secure Computing, 16th Intl Conf on Pervasive Intelligence and Computing, 4th Intl Conf on Big Data Intelligence and Computing and Cyber Science and Technology Congress (DASC/PiCom/DataCom/CyberSciTech)

Abstract:- Owing to the condensed size of components in digital designs on the FPGA, it is difficult to guarantee an acceptable degree of reliability due to soft-errors. These designs are mostly available in Hardware Description Languages (HDL) at various abstraction levels, e.g. gate-level, data-flow, and behavioural. Fault Injection (FI) is a well-known technique to assess the dependability of such designs. Broadly, FI techniques for FPGA-based designs are categorized into emulation and simulation-based techniques. Simulation-Based FI (SBFI) tools work on hardware models of designs and help designers to test and verify designs at an early phase of the FPGA design & development flow. Testing, dependability analysis, and fault simulation applications require a faulty model of the original design during fault injection campaign. Therefore, we require a tool which can automatically generate the faulty model of the original design written at any abstraction levels and perform fault injection testing and dependability analysis. In this paper, a fault injection tool (RASP-FIT) is presented, which consists of an automatic code modifier (fault injection algorithm), fault injection control unit and result analyser. Previously, the tool is used for code-modification, test and hardness analysis for gate-level designs. In this paper, an enhancement of a code modifier along with result analyser techniques are applied to the data-flow benchmark designs and presented.

Conference Details:- 2017 First International Conference on Latest trends in Electrical Engineering and Computing Technologies (INTELLECT).

Abstract:- SRAM-based FPGA covers nearly 60% of the applications, also susceptible to Single Event Upsets (SEUs) due to radiation. Therefore, FPGA-based systems need to be tested and verified. The testing and dependability analysis techniques are most widely used, with fault injection techniques. These approaches are developed in RASP-Fault Injection Tool. These approaches require the deliberate introduction of faults in the target system. In test approach, it is mandatory to obtain minimum test vectors which detect maximum faults. There are many fault models used for that purpose, e.g. bit-flip, stuck-at (1 & 0). In the proposed test approach, the condition of set point value (SP-value) is defined for each fault model. Therefore, the only patterns which can detect faults more than SP-value are collected and called them qualified test vectors. Furthermore, these qualified vectors are used to obtain the compact test vectors for the Automatic Test Equipment (ATE). In our previously proposed test method, we have used the concept of the SP-value method to obtain qualified test vector for FPGA-based designs. We have chosen SP-values in the range of 20% to 50% of the total injected faults in the design. However, in this paper, validation of this selection criterion for the SP-value is presented.

Conference Details:- 2017 International Symposium on Applied Reconfigurable Computing.

Abstract:- Dependability analysis and test approaches are key steps in order to test and verify system robustness and fault-tolerance capabilities. Owing to the shrinking size of components, it is very difficult to guarantee an acceptable degree of reliability. With the growing computational power of FPGAs and other diverse advantages, they have become indispensable solutions for embedded applications. However, these systems are also prone to faults and errors. Therefore, the testability and the dependability analysis are necessary. Both methods require the deliberate introduction of faults in the SUT. In this paper, a fault injection algorithm is proposed for Verilog gate level code, which injects faults in the design. Also, the method is proposed for finding sensitive locations of SUT. These methods are developed under a fault injection tool, with a GUI, for the ease of use, and it is named RASP-FIT tool. Benchmark circuits from ISCAS’85 and ISCAS’89 are considered to validate the both proposed methods.

Conference Details:- 2016 SAI Computing Conference (SAI).

Abstract:- In this paper, the Test Pattern Generation (TPG) with a new simple hybrid (dynamic and static) compaction technique for combinational logic circuits and systems is presented. Digital systems are implemented nowadays on an advance VLSI technology, which is called Field Programmable Gate Array (FPGA). The test procedure requires a deliberate introduction of faults in the System Under Test (SUT). FPGA circuits and systems are developed and written in Hardware Description Languages (HDLs). In addition, a novel method is also proposed and implemented in order to intentionally inject faults in the Verilog HDL code design of the SUT. It covers all possible fault locations in the SUT. This approach provides high quality compact test vectors and efficient memory utilization in comparison with other state-of-the-art methods. Not only are the hardness of individual faults and the sensitiveness of fault locations determined, but also their effectiveness is proposed in the fault tolerance strategy.

Conference Details:- Recent Advances in Financial Planning and Product Development.

Abstract:- This paper presents an overview about FPGA based fault injection tools which are developed by using the instrumentation technique or modification in the original code. The fault injection technique is used to evaluate dependability parameters of computer-based embedded systems or safety-critical systems, by injecting faults in a system. An observation on the behaviour or of the response for both-fault free and faulty systems-is made and the results are matched. In the instrumentation based technique, faults are injected by adding some additional circuits in the target system known as fault models. Different fault models are explained in this paper, e.g. Stuck at 0/1, Bit flip, Mutant and Saboteur. A variety of FPGA based tools are discussed and a new FPGA based fault injection technique is introduced. The tool that has been developed according to our methodology can work on any simple or complex digital circuits or SoC realized on FPGA. This can be exercised to evaluate the dependability parameters for the target systems under test e.g. fault coverage, fault latency and reliability.