MEMBER

Younghoon Byun

Ph.D. Candidate, 

Department of Electrical Engineering,

Pohang University of Science and Technology (POSTECH)

Google scholar : https://scholar.google.co.kr/citations?user=HPjYROIAAAAJ&hl=ko

Contact Information

• Address : #308, Science Building II, POSTECH, Pohang, Korea

• Email : byh1321[at]postech.ac.kr

• Office : +82-(0)54-279-5587

Educational Backgrounds

• [2020/09~Present] Ph.D. Candidate in Electrical Engineering, POSTECH, Pohang, Korea

• [2018/02~2020/02] M.S. in Electrical Engineering, POSTECH, Pohang, Korea

• [2011/03~2018/02] B.S. in Electrical Engineering, POSTECH, Pohang, Korea

Professional Experiences

• [2020/02~2020/09] Research Assistant, Dept. Electrical Engineering, POSTECH, Pohang, Korea

• [2017/06~2018/02] Research Assistant, Dept. Electrical Engineering, POSTECH, Pohang, Korea

• [2016/06~2016/08] Internship, ETRI, Daejeon, Korea

• [2015/12~2016/02] Internship, SK Hynix, Icheon, Korea

Research Interests

• Intelligent Mobile System-on-Chip

• Deep Learning Model Compression

• Deep Learning Hardware-Software Co-optimization

Publications

• International Journal Papers

  1. Hyeokjun Kwon, Younghoon Byun, Seokhyeong Kang, and Youngjoo Lee*, "CHAMP: Channel merging process for cost-efficient highly-pruned CNN acceleration," IEEE Transactions on Circuits and Systems I: Regular vol. 69, no. 8, pp. 3308-3319, Aug. 2022.

  2. Minho Ha, Younghoon Byun, Seungsik Moon, Youngjoo Lee, and Sunggu Lee*, "Layerwise buffer voltage scaling for energy-efficient convolutional neural network," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 40, no. 1, pp. 1-10, Jan. 2021.

  3. Seungsik Moon+, Younghoon Byun+, Jongmin Park, Sunggu Lee, and Youngjoo Lee*, "Memory-reduced network stacking for edge-level CNN architecture with structured pruning," IEEE Journal on Emerging and Selected Topics in Circuits and Systems, vol. 9, no. 4, pp. 735-746, Dec. 2019. (Invited)

  4. Minho Ha, Younghoon Byun, Jeonghun Kim, Jaecheol Lee, Youngjoo Lee, and Sunggu Lee, “Selective Deep Convolutional Neural Network for Low Cost Distorted Image Classification,” IEEE Access, 2019, 133030-133042.

• International Conference Proceedings

  1. Younghoon Byun and Youngjoo Lee*, "Partially-Structured Transformer Pruning with Patch-Limited XOR-Gate Compression for Stall-Free Sparse-Model Access," Design Automation Conference (DAC), San Francisco, CA, USA, June 2024 .

  2. Jung Gyu Min, Dongyun Kam, Younghoon Byun, Gunho Park, and Youngjoo Lee*, "Energy-efficient RISC-V-based vector processor for cache-aware structurally-pruned transformers," ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED), Vienna, Austria, Aug. 2023.

  3. Younghoon Byun+, Seungsik Moon+, Baeseong Park, Se Jung Kwon, Dongsoo Lee, Gunho Park, Eunji Yoo, Jung Gyu Min, and Youngjoo Lee*, "Sparsity-aware memory interface architecture using stacked XORNet compression for accelerating pruned-DNN models," Conference on Machine Learning and Systems (MLSys), Miami, FL, USA, June 2023. 

  4. Younghoon Byun and Youngjoo Lee*, "Rapid design space exploration of near-optimal memory-reduced DCNN architecture using multiple model compression techniques," IEEE International Symposium on Circuits and Systems (ISCAS), Daegu, Korea, May 2021, pp. 1-5.

  5. Yesung Kang, Eunji Kwon, Seunggyu Lee, Younghoon Byun, Youngjoo Lee, and Seokhyeong Kang*, "Approach to improve the performance using bit-level sparsity in neural networks," IEEE/ACM Design, Automation and Test in Europe (DATE), Feb. 2021. 

  6. Seungsik Moon, Hyunhoon Lee, Younghoon Byun, Jongmin Park, Junseo Joe, Seokha Hwang, Sunggu Lee, and Youngjoo Lee*, "FPGA-based sparsity-aware CNN accelerator for noise-resilient edge-level image recognition," IEEE Asian Solid-State Circuits Conference (A-SSCC), Macao, China, Nov. 2019, pp. 205-208. (Distinguished Design Award) 

  7. Jongmin Park, Seungsik Moon, Younghoon Byun, Sunggu Lee, and Youngjoo Lee*, "Multi-level weight indexing scheme for memory-reduced convolutional neural network," IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS), Hsinchu, Taiwan, Mar. 2019, pp. 284-287. 

  8. Younghoon Byun, Minho Ha, Jeonghun Kim, Sunggu Lee, and Youngjoo Lee*, "Low-complexity dynamic channel scaling of noise-resilient CNN for intelligent edge devices," IEEE/ACM Design, Automation and Test in Europe (DATE), Florence, Italy, Mar. 2019, pp. 114-119. 

  9. Hyunhoon Lee, Younghoon Byun, Seokha Hwang, Sunggu Lee, and Youngjoo Lee*, "Fixed-point quantization of 3D convolutional Neural Networks for energy-efficient action recognition," International SoC Design Conference (ISOCC), Daegu, Korea, Nov. 2018, pp. 129-130. 

• Domestic Journal Papers

  1. 변영훈, 조준서, 이영주*, "효율적 메모리 관리를 통한 모바일 CNN 가속기의 최적화," 전자공학회지, vol. 45, no. 1, pp. 28-34, Jan. 2018.

• Domestic Conference Proceedings

  1. 변영훈, 이영주*, "64bit RISC-V 기반 칩 검증 플랫폼 설계," 제 29회 한국반도체학술대회, Jan. 2022.

  2. 조준서, 변영훈, 이영주*, "인공 신경망의 데이터 정밀도와 인식률 간의 관계에 대한 연구," 제 25회 한국반도체학술대회, Feb. 2018, pp. 792.

• Patents

  1. Youngjoo Lee, Sunggu Lee, Minho Ha, and Younghoon Byun, "Neural processing device and operation method thereof," 8947NS-001411-US.

  2. 이영주, 이승구, 하민호, 변영훈, "뉴럴 프로세싱 장치 및 그것의 동작 방법," 등록번호: 10-2135632, 출원번호: 10-2018-0116612.

Awards and Honors

• Special Award (기업특별상), 21st Korea Semiconductor Design Contest, 2020.

• Distinguished Design Award, IEEE Asian Solid-State Circuits Conference (A-SSCC), 2019.