MEMBER

Jeongwon Choe, Ph.D.

Postdoc Researcher,

School of Electrical Engineering,

Korea Advanced Institute of Science and Technology (KAIST)

Contact Information

• Address : #4219, Information & Electronics Building (E3-2), KAIST, Daejeon, Korea

• Email : choejw[at]kaist.ac.kr (or choejw.epiclab[at]gmail.com)

• Office : +82-(0)42-350-7579

Educational Backgrounds

• [2022/02~2025/08] Ph.D. in Electrical Engineering, POSTECH, Pohang, Korea

• [2020/02~2022/02] M.S. in Electrical Engineering, POSTECH, Pohang, Korea

• [2016/03~2020/02] B.S. in Electrical Engineering, POSTECH, Pohang, Korea

Professional Experiences

• [2025/09~Present] Postdoc Researcher, Sch. Electrical Engineering, KAIST, Daejeon, Korea

• [2025/03~2025/08] Visiting Researcher, Sch. Electrical Engineering, KAIST, Daejeon, Korea

• [2018/12~2025/08] Research Assistant, Dept. Electrical Engineering, POSTECH, Pohang, Korea

Research Interests

• Intelligent Mobile System-on-Chip

• Error Correction Code (ECC) for mobile systems

• ASIC/FPGA Implementation

• 5G Communication systems

Publications

• International Journal Papers

  1. Jeongwon Choe and Youngjoo Lee*, "Area-efficient non-binary LDPC decoder with column-wise trellis min-max algorithm," IEEE Journal of Solid-State Circuits, vol. 60, no. 3, pp. 1082-1091, Mar. 2025.

  2. Sangbu Yun+, Jeongwon Choe+, and Youngjoo Lee*, "High-throughput software-defined LDPC encoder and decoder with x86-based data-level parallelism," IEEE Transactions on Vehicular Technology, vol. 74, no. 1, pp. 50-60, Jan. 2025.

  3. Dain Park, Dongyun Kam, Sangbu Yun, Jeongwon Choe, and Youngjoo Lee*, "Hard-decision SCL polar decoder with weighted pruning operation for storage applications," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 71, no. 9, pp. 4181-4185, Sep. 2024.

  4. Jeongwon Choe and Youngjoo Lee*, "High-throughput non-binary LDPC decoder architecture using parallel EMS algorithm," IEEE Journal of Solid-State Circuits, vol. 57, no. 10, pp. 2969-2978, Oct. 2022. (Invited)

  5. Seungwoo Hong, Dongyun Kam, Sangbu Yun, Jeongwon Choe, Namyoon Lee, and Youngjoo Lee*, "Low-complexity and low-latency SVC decoding architecture using modified MAP-SP algorithm," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 69, no. 4, pp. 1774-1787, Apr. 2022.

  6. Seungsik Moon, Jeongwon Choe, and Youngjoo Lee*, "Low-latency unfolded-KES architecture for emerging storage class memories," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 67, no. 6, pp. 2103-2113, June 2020.

• International Conference Proceedings

  1. Seungjun Kim, Jeongwon Choe, and Youngjoo Lee*, "On the decoding complexity of error correction code transformer," International Conference on ICT Convergence (ICTC), Jeju, Korea, Oct. 2024.

  2. Jeongwon Choe and Youngjoo Lee*, "Cost-efficient partially-parallel LDPC decoder architecture for 50G-PON standard," International SoC Design Conference (ISOCC), Sapporo, Japan, Aug. 2024.

  3. Dongyun Kam, Sangbu Yun, Jeongwon Choe, Zhengya Zhang, Namyoon Lee, and Youngjoo Lee*, "A 21.9 ns, 15.7 Gbps/mm^2 (128, 15) BOSS FEC decoder for 5G/6G URLLC applications," IEEE International Solid-State Circuits Conference (ISSCC), San Francisco, CA, USA, Feb. 2024.

  4. Jeongwon Choe and Youngjoo Lee* "A 2.35 Gb/s/mm^2 (7440, 6696) NB-LDPC decoder over GF(32) using memory-reduced column-wise trellis min-max algorithm in 28nm CMOS technology," IEEE Symposium on VLSI Technology and Circuits (VLSI), Kyoto, Japan, June 2023.

  5. Jeongwon Choe and Youngjoo Lee*, "A 7Gbps (160, 80) non-binary LDPC decoder with dual-message EMS algorithm in 22nm FinFET Technology," IEEE Asian Solid-State Circuits Conference (A-SSCC), Busan, Korea, Nov. 2021.

  6. Changhyeon Kim, Dongyoung Rim, Jeongwon Choe, Dongyun Kam, Giyoon Park, Seokki Kim, and Youngjoo Lee*, "FPGA-based ordered statistic decoding architecture for B5G/6G URLLC IIOT networks," IEEE Asian Solid-State Circuits Conference (A-SSCC), Busan, Korea, Nov. 2021.

  7. Sangbu Yun, Dongyun Kam, Jeongwon Choe, Byeong Yong Kong, and Youngjoo Lee*, "Ultra-low-latency LDPC decoding architecture using reweighted offset min-sum algorithm," IEEE International Symposium on Circuits and Systems (ISCAS), Seville, Spain, Oct. 2020, pp. 1-5. 

• Domestic Conference Proceedings

  1. 최정원, 김광옥, 두경환, 정환석, 이영주*, "50G-PON 용 LDPC 부호기 FPGA 구현," 제 31회 한국반도체학술대회, Jan. 2024, pp. 665. (우수포스터상)

  2. 최정원, 이영주*, "스토리지 용 NB-LDPC 복호기 하드웨어 개발," 반도체공학회 종합학술대회, Dec. 2023. (우수논문상)

  3. 윤상부, 최정원, 김석기, 김남일, 이영주*, "소프트웨어 모뎀을 위한 LDPC 부/복호기의 병렬화," 2022년도 반도체공학회 하계학술대회, July 2022.

  4. 최정원, 이영주*, "인공 신경망 기반 고성능 LDPC 복호화 기법," 제 27회 한국반도체학술대회, Feb. 2020, pp. 538.

• Patents

  1. Seokki Kim, Namil Kim, Sangbu Yun, Youngjoo Lee, Jeongwon Choe, "LDPC encoding and decoding method," Application Number: US18/396,774.

  2. 김석기, 김남일, 윤상부, 이영주, 최정원, "저밀도 패리티 체크 부복호화 방법," 출원번호: 10-2023-0191154.

  3. Youngjoo Lee, Young-Seok Kim, and Jeongwon Choe, "Non-binary low density parity check codes and decoding method using the same," PCT/KR2020/016696. 

  4. 이영주, 김영석, 최정원, "비이진 저밀도 패리티 검사 코드 복호기 및 이를 이용한 복호화 방법," 등록번호: 10-2476160, 출원번호: 10-2020-0150417. 

Awards and Honors

• Best Poster Award, 제 31회 반도체학술대회, 2024.

• Best Paper Award, Annual Conference of ISE, 2023.

• Best Paper Award, Samsung-POSTECH Research Center, 2023.

• Excellence Design Award, POSTECH BMSC Chip Design Contest, 2023.