MEMBER

Eunbin Park 

Ph.D. Student,

Department of Electrical Engineering,

Pohang University of Science and Technology (POSTECH)

Contact Information

• Address : #4219, Information & Electronics Building (E3-2), KAIST, Daejeon, Korea

• Email : eunbin[at]postech.ac.kr (or eunbin.epiclab[at]gmail.com)

• Office : +82-(0)42-350-7579

Educational Backgrounds

• [2024/03~Present] Ph.D. Candidate in Semiconductor Engineering, POSTECH, Pohang, Korea

• [2022/02~2024/02] M.S. in Electrical Engineering, POSTECH, Pohang, Korea

• [2018/03~2022/02] B.S. in Electrical and Computer Engineering, Kyungpook National University, Daegu, Korea

Professional Experiences

• [2025/08~Present] Visiting Researcher, Sch. Electrical Engineering, KAIST, Daejeon, Korea

• [2022/02~Present] Research Assistant, Dept. Electrical Engineering, POSTECH, Pohang, Korea 

Research Interests

• Intelligent Mobile System-on-Chip

• Network on Chip system design

• Privacy-Preserving Deep Learning 

• HW/SW Co-design

Publications

• International Journal Papers

  1. E. Park and Y. Lee, "mDARTS: Searching ML-Based ECG Classifiers Against Membership Inference Attacks," in IEEE Journal of Biomedical and Health Informatics, vol. 29, no.1, pp.177-187, Jan. 2025, doi:10.1109/JBHI.2024.3481505.

  2. E. Park and T. Song, "Complementary FET (CFET) Standard Cell Design for Low Parasitics and Its Impact on VLSI Prediction at 3-nm Process," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2022, doi: 10.1109/TVLSI.2022.3220339. 

• International Conference Proceedings

  1. Yeji Lee+, Eunbin Park+, and Youngjoo Lee*,  "AMC: Adaptive mixed compression for ML models based on block-wise sensitivity," IEEE International Symposium on Circuits and Systems (ISCAS), London, UK, May 2025.

  2. Eunbin Park, Myungjun Jin, and Youngjoo Lee*, "Cost-efficient SIMD ASIP architecture for mobile touchscreen controllers," IEEE International Symposium on Circuits and Systems (ISCAS), Singapore, Singapore, May 2024.

  3. Eunbin Park and Taigon Song*, “An Optimized Standard Cell Design Methodology Targeting Low Parasitics and Small Area for Complementary FETs (CFETs),”  IEEE International SoC Design Conference (ISOCC), 2021. 

• Domestic Conference Proceedings

  1. Eunbin Park, and Taigon Song*, “Standard Cell Design Methodology for Complementary FETs (CFETs),” The 29th Korea Conference on Semiconductors, 2022