KAIST EPIC Lab

Welcome to EPIC LAB at KAIST EE/AIS

Embedded Processor & Intelligent Computing (EPIC) Lab is a research group at the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, jointly affiliated with the School of Electrical Engineering and the Department of AI Systems. EPIC Lab develops efficient hardware-software building blocks for application-specific embedded processors, with a focus on intelligent computing across a broad range of emerging workloads.

Our research spans cross-disciplinary topics including algorithms, computer architectures, and system-on-chip (SoC) designs. We currently focus on energy-efficient processors for compressed machine learning models, high-performance baseband processors for next-generation communication systems, and emerging IoT platforms for human-centric applications.

Latest News

[2026/04] Our paper entitled "Machine learning assisted tilt/azimuth estimation for passive stylus pens using position-based model selection" has been accepted for publication in the IEEE Access.

[2026/04] Our paper entitled "StylusNet: ML-based coordinate extractor for EMR stylus touch devices" has been accepted for publication in the IEEE Sensors Journal.

[2026/03] Prof. Lee has received the Outstanding Lecture Award from KAIST EE.

[2026/03] Our paper entitled "CL-PLAC: A generalized design framework for nonlinear functions using comparator-less piecewise linear approximate computation" has been accepted for publication in the IEEE Transactions on Circuits and Systems for Artificial Intelligence.

[2026/02] Our paper entitled "Asymmetric KV cache compression using state-aware sparsity and quantization" has been accepted for publication in the IEEE Transactions on Circuits and Systems for Artificial Intelligence.

[2026/01] Our paper entitled "Memory-efficient partially self-corrected min-sum LDPC decoder for 5G NR applications" has been accetped for presentation at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS 2026).

[2026/01] Our paper entitled "Memory-efficient twiddle factor generator in parallel NTT accelerators for FHE applications" has been accetped for presentation at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS 2026).

[2026/01] Our paper entitled "Low-latency software-defined 5G NR PUSCH receiver with mixed-precision SIMD acceleration" has been accetped for presentation at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS 2026).

[2026/01] Our paper entitled "A parametric power model of upper mid-band (FR3) base stations for 6G" has been accepted for presentation at the 2026 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2026).