KAIST EPIC Lab

Welcome to EPIC LAB at KAIST EE

Embedded Processor & Intelligent Computing (EPIC) Lab is a research group in the School of Electrical Engineering at Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea. With a passionate team, EPIC Lab develops optimized hardware/software building blocks for modern application-specific embedded processors targeting a wide range of intelligent computing workloads.

Our research spans cross-disciplinary topics including algorithms, architectures, and system-on-chip (SoC) designs. Current focus areas include advanced deep learning processors for compressed machine learning models, high-performance baseband processors for next-generation communication systems, and energy-efficient IoT platforms for human-centric applications.

Latest News

[2025/08] Our paper entitled "FPGA-based real-time ISP accelerator using low-cost line buffers and non-linear functions" has been accepted for presentation at the 2025 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2025).

[2025/08] Our paper entitled "A quantitative evaluation method of neural rendering accelerators" has been accepted for presentation at the 2025 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS 2025).

[2025/08] Our paper entitled "On the hardware efficiency of short-length polarization-adjusted convolutional polar decoders" has been accepted for presentation at the 2025 IEEE Asia Pacific Conference of Circuits and Systems (APCCAS 2025).

[2025/08] Our paper entitled "Hybrid ordered statistics decoding of short-length BCH codes for URLLC systems: Theoretical analysis and decoder implementation" has been accepted for presentation at the 2025 IEEE International Symposium on Integrated Circuits and Systems (ISICAS 2025, TCAS-I Special Issue). 

[2025/07] Our paper entitled "A lightweight ML-based ECG classification system using self-personalized anomaly detector" has been accepted for publication in the IEEE Journal of Biomedical and Health Informatics.

[2025/06] Our research on the universal error compensation for PIM architectures has been selected as the Best Paper Award Candidate at the 2025 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED 2025).

[2025/05] Our paper entitled "Ultra-fast CV-ECRAM-based analog PIM with dynamic retention compensation techniques" has been accepted for presentation at the 2025 IEEE European Solid-State Electronics Research Conference (ESSERC 2025). 

[2025/05] Our paper entitled "Cost-efficient processing-in-memory architecture with training-free and universal error compensation" has been accepted for presentation at the 2025 ACM/IEEE International Symposium on Low Power Electronics and Design (ISLPED 2025).

[2025/05] Our paper entitled "Hybrid ordered statistics decoding of short-length BCH codes for URLLC systems: Theoretical analysis and decoder implementation" has been accepted for publication in the IEEE Transactions on Circuits and Systems I: Regular Papers.