KAIST EPIC Lab

Welcome to EPIC LAB at KAIST EE

Embedded Processor & Intelligent Computing (EPIC) Lab is a research group in the School of Electrical Engineering at Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea. With a passionate team, EPIC Lab develops optimized hardware/software building blocks for modern application-specific embedded processors targeting a wide range of intelligent computing workloads.

Our research spans cross-disciplinary topics including algorithms, architectures, and system-on-chip (SoC) designs. Current focus areas include advanced deep learning processors for compressed machine learning models, high-performance baseband processors for next-generation communication systems, and energy-efficient IoT platforms for human-centric applications.

Latest News

[2026/01] Our paper entitled "Memory-efficient partially self-corrected min-sum LDPC decoder for 5G NR applications" has been accetped for presentation at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS 2026).

[2026/01] Our paper entitled "Memory-efficient twiddle factor generator in parallel NTT accelerators for FHE applications" has been accetped for presentation at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS 2026).

[2026/01] Our paper entitled "Low-latency software-defined 5G NR PUSCH receiver with mixed-precision SIMD acceleration" has been accetped for presentation at the 2026 IEEE International Symposium on Circuits and Systems (ISCAS 2026).

[2026/01] Our paper entitled "A parametric power model of upper mid-band (FR3) base stations for 6G" has been accepted for presentation at the 2026 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP 2026).

[2025/11] Our paper entitled "LUT-SSM: A 99.3TFLOPS/W LUT-based state-space model accelerator using energy-efficient element-wise layer fusion and LUT-friendly weight-only quantization" has been accepted for presentation at the IEEE International Solid-State Circuits Conference (ISSCC 2026).

[2025/11] Our paper entitled "UniC-Vision: A 14.4Gb/s 7.3pJ/b universal vision transformer OFDM channel estimation accelerator for B5G/6G AI-RAN" has been accepted for presentation at the IEEE International Solid-State Circuits Conference (ISSCC 2026).

[2025/11] Our paper entitled "A 1.1mm^2, 14.4ns, 13.1pJ/b forward error correction with ordered-statistics post processing for ultra-reliable and low-latency communications" has been accepted for presentation at the IEEE International Solid-State Circuits Conference (ISSCC 2026).

[2025/11] Our paper entitled "IterQuant: Iterative quantization framework for mixed-precision LLM compression" has been accepted for presentation at the IEEE/ACM Design, Automation and Test in Europe (DATE 2026).

[2025/11] Our paper entitled "A 3.3 Gb/s/mm^2 area-efficient non-binary LDPC decoder using column-layered processing" has been accepted for publication in the IEEE Transactions on Circuits and Systems I: Regular Papers.