Lab 1: Seven Segment Decoder

Introduction:

The purpose of this lab is to introduce you to the NEXYS4 DDR FPGA development board and a software environment that will allow you to design a hardware system in VHDL, synthesize your design to create an FPGA configuration file, download the configuration file on to an FPGA and then run the configured FPGA to achieve the desired hardware functionality.

Connecting and Testing the Nexys Board :

1. Connect the board to your machine using the supplied USB cord and turn the power switch on.
2. Start the Adept Software
   • Software can be found here
3. Select the Test tab and click Start Test
4. Ensure that all tests are marked as pass

LED Decoder :

1. Start the Vivado program
   • This group used Vivado 2018.2
2. Create a New Project and name is leddec
   1. File -> New Project
   2. Leave Project type as RTL and do not specify sources as this time
   3. Default part is XC7A100TCSG324
      • This team chose XC7A100TCSG324-1 as the default part
3. Now create a new VHDL source
   1. File -> Add Sources
   2. Select "Add or create design sources" and Next
   3. Click the "+" and then "Create File"
   4. Ensure the File Type is set to VHDL and name the file "leddec"
   5. Replace the default code with the code in leddec.vhd.pdf
4. Click Run Synthesis and allow it to finish
5. Next create a constraint file
   1. File -> Add Sources
   2. Select "Add or create constraints" and Next
   3. Click the "+" and then "Create File"
   4. Ensure the File Type is set to XDC and name the file "leddec.xdc"
   5. Replace the default code with the code in leddec.xdc.pdf
6. Click Run Implementation and allow it to finish
7. Once the Implementation is finished, select Generate Bitstream
8. Plug in the device if it is not already and Vivado should detect the board
9. Click program device and load the generated bitstream onto the board

Hex Counter :

1. Start the Vivado program
   • This group used Vivado 2018.2
2. Create a New Project and name is hexcounter
   1. File -> New Project
   2. Leave Project type as RTL and do not specify sources as this time
   3. Default part is XC7A100TCSG324
      • This team chose XC7A100TCSG324-1 as the default part
3. Now create a new VHDL source and add the existing leddec.vhd
   1. File -> Add Sources
   2. Select "Add or create design sources" and Next
   3. Click the "+" and then "Add files"
   4. Select leddec.vhd from where it is stored on your machine (should be in the sources folder.
   5. Click finish
4. Then Create two new VHDL files (in similar to step 3 but click "Create files")
   1. The first should be named counter.vhd and should contain the code from counter.vhd.pdf
   2. The second file should be named hexcount.vhd and should contain the code from hexcount.vhd.pdf
      • Once this file is created, look for it in the sources window and right click it.
      • If the file is not already Set as Top click that option
5. Next create a constraint file
   1. File -> Add Sources
   2. Select "Add or create constraints" and Next
   3. Click the "+" and then "Create File"
   4. Ensure the File Type is set to XDC and name the file "hexcount.xdc"
   5. Replace the default code with the code in hexcount.xdc.pdf
6. Click Run Synthesis and allow it to finish (status on top right of window)
7. Click Run Implementation and allow it to finish
8. Once the Implementation is finished, select Generate Bitstream
9. Plug in the device if it is not already and Vivado should detect the board
10. Click program device and load the generated bitstream onto the board

Helpful Resources:

How to set up the bitstream:

http://users.wpi.edu/~rjduck/Nexys4DDR%20Vivado%20VHDL%20Decoder%20Tutorial.pdf

How to Connect The Nexys A7 to your computer:

https://github.com/Digilent/Nexys-A7-100T-GPIO

Dr. Ackland's Lab Manual:

http://personal.stevens.edu/~backland/Courses/Course487_Spring_18_files/Labs/Lab1.pdf

GitHub:

https://github.com/kevinwlu/dsd