Full Adder Test Bench

adder.vhdl

adder_tb.vhdl

Introduction:

This objective of this bonus lab is to simulate a Full Adder within the Vivado application.

Step:

Create a VHDL design source named adder
Then Create a VHDL simulation source named adder_tb
Now there is no need to Run the Synthesis or Implementation
Click Run Simulation
1. Then Click Run Behavioral Simulation

Results:

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