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Abstract
Phase Change Memory (PCM) has presented as a potential replacement of DRAM due to its better scalability. However, MLC PCM encounters reliability problems such as resistance drift error and cell wear-out. To improve reliability, implementing strong Error Correction Codes (ECC) is required but this incurs substantial overhead to memory system. Existing ECC schemes have trade-offs between error correction capability and overhead. This paper proposes Single Cell Correction (SCC) codes, an efficient ECC scheme which can correct single cell errors in MLC PCM with small overhead.
Proposed Method
SCC uses 7-bit redundancy over 64-bit data, like SEC. This allows for 127 non-zero syndromes, of which 106 (71 single-bit error + 35 single-cell error) are mapped to single bit or single cell error cases. Syndromes were generated over GF(27) with a specific polynomial, and 106 were chosen as column vectors in the H-matrix to meet the following conditions.
All column vectors are nonzero.
All column vectors are unique.
For two adjacent column vectors, with the left in an odd column and the right in an even, their sum must be unique.
Figure 1. H-matrix example of SCC code with generator polynomial=0xE5.
Result
MLC PCM can improve storage density without scalability limitations, but it faces significant reliability issues. Using ECC can enhance reliability, while it comes with a substantial overhead. This paper introduces an efficient ECC code, SCC, which can correct up to a 1-cell error. Given the frequent error patterns in MLC PCM, the proposed scheme is the optimal solution to protect PCM memory.
Table 1. Reliability comparison between existing ECC schemes and SCC in MLC PCM.
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