Wireline Networking Area (유선망 분야)

Wireline Networking Area


We had extensive studies on high performance multiservice and IP networking in terms of the following research issues:


■System Level Simulators for Performance Evaluation



Fig. 1 ASIC Chip of Quasi-Shared Buffer ATM Switch

Fig. 2 Decomposed Crossbar Switch Board

(1) Selected Papers

       <Multiservice Switch Architecture>


  <Traffic Modeling>

   <Traffic Control/Priority Scheduling>

   <Bandwidth Estimation & Control>

         <Call Admission Control>

    <QoS Estimation & Monitoring>

   <Traffic Generation and Monitoring>

    <Signaling Networks/Intelligent Networks>


 <Performability of Communication Networks>



         <Switch/Router Simulators for Performance Evaluation>


 

(2)  Conference Papers

(3)  Patents

(4)  Book/Book Chapter in ATM Networks

 

      (5) Major Research Projects