Biography
I am Daichi Tokuda (篤田大知), and I am a second-year master's student at the University of Tokyo.
My research interests are:
･ Computer Architecture
･ Memory System
･ Efficient Hardware Accelerator
･ Processing-In-Memory
･ Benchmarking and Modeling for Computer System
･ Explore System Architecture
Education
2020/04 - : The University of Tokyo.
2022/04 - 2024/03: Department of Information Science at the Faculty of Science, The University of Tokyo.
2024/04 - : Department of Computer Science, Graduate School of Information Science and Technology, The University of Tokyo
2024/09 - 2025/02: Exchange Student at Swiss Federal Institute of Technology in Zurich (ETH)
Research Experience
･Research experience supervised by Prof. Shinya Takamaeda-Yamazaki. (2023/04-)
･Research experience supervised by Prof. Onur Mutlu. (2024/09-)
Publication
Peer-Reviewed Conferences & Journals
･Daichi Tokuda, Ismail Emir Yuksel, Tatsuya Kubo, Ataberk Olgun, Haocong Luo, Nisa Bostanci, Jikun Wang, Abdullah Giray Yağlıkçı, Shinya Takamaeda-Yamazaki, and Onur Mutlu, "PuDGhost: Experimental Analysis of Computation Result Corruption in Processing-using-DRAM Operations on Real DRAM Chips and Implications for Future Systems", 53rd Annual International Symposium on Computer Architecture (ISCA 2026, To Appear), June 2026.
･Daichi Tokuda, T. Kubo, I. Yuksel, A. Olgun, H. Luo, T. Nagatani, G. De Oliveira Junior, A. Yağlıkçı, M. Sadrosadati, O. Mutlu, S. Takamaeda-Yamazaki, "Clutch: High Performance Vector-Scalar Comparison using DRAM via Chunked Temporal Coding", International Conference on Supercoputing (ICS 2026, To Appear), July 2026. <paper link>
･Daichi Tokuda and Shinya Takamaeda-Yamazaki, "An FPGA-based Memory Locality Aware Decision Forest Accelerator via Bit-Level Early Termination", ACM Transactions on Reconfigurable Technology and Systems Vol.18, Issue.2, pp.1-26 (ACM TRETS), March 2025. <paper link>
･Tatsuya Kubo, Masayuki Usui, Tomoya Nagatani, Daichi Tokuda, Lei Qu, Ting Cao, and Shinya Takamaeda-Yamazaki, "Bulk Bitwise Accumulation in Commercial DRAM", NeurIPS 2024 Workshop Machine Learning with new Compute Paradigms (MLNCP 2024), December 2024. <paper link>
･Tatsuya Kubo, Daichi Tokuda, Lei Qu, Ting Cao, and Shinya Takamaeda-Yamazaki, "PUDTune: Multi-Level Charging for High-Precision Calibration in Processing-Using-DRAM", IEEE Computer Architecture Letters (CAL), June 2025, Accepted. <paper link>
Workshop & Posters
･Daichi Tokuda, Ismail Emir Yuksel, Tatsuya Kubo, Ataberk Olgun, Haocong Luo, Nisa Bostanci, Jikun Wang, Abdullah Giray Yağlıkçı, Shinya Takamaeda-Yamazaki, and Onur Mutlu, "PuDGhost: Experimental Analysis of Computation Result Corruption in Processing-using-DRAM Operations on Real DRAM Chips and Implications for Future Systems", 7th Workshop on Memory-Centric Computing Systems (MCCSys), July 2026.
･Daichi Tokuda, Shinya Takamaeda-Yamazaki, "Hardware/Algorithm Co-design for Gradient Boosting Decision Trees via Bit-Level Early-Termination for Embedded Systems” (xSIG 2024) Outstanding Research Award 2024/8/7
･Daichi Tokuda, Shinya Takamaeda-Yamazaki, "Decision Forest Accelerator via Bit-level Early Termination" (ForestWorkshop 2023) 2024/3/30
Award
･Outstanding Research Award: Daichi Tokuda, Shinya Takamaeda-Yamazaki, "Hardware/Algorithm Co-design for Gradient Boosting Decision Trees via Bit-Level Early-Termination for Embedded Systems” (xSIG 2024)
･Outstanding Young Researcher Presentation Award, Technical Committee on Computer Systems, The Institute of Electronics, Information and Communication Engineers (IEICE), for “Experimental Analysis of Non-Input Data Pattern Dependence in Processing-using-DRAM,” Mar. 2026.
･Invited Talk: Daichi Tokuda, "Hardware/Algorithm Co-design for Gradient Boosting Decision Trees via Bit-Level Early-Termination for Embedded Systems" (FIT 2025)
･Invited Talk: Daichi Tokuda, "PuDGhost: Experimental Analysis of Computation Result Corruption in Processing-using-DRAM Operations on Real DRAM Chips and Implications for Future Systems" (FIT 2026)
Professional skill
･Hardware Description Languages (System Verilog, Verilog)
･FPGA Development (Vivado, Vitis AI)
･C, CPP ( Operating System development, etc.)
･Python (Machine Learning, Pytorch, etc.)