PhD Thesis: Compact Modeling of FinFET and FDSOI FET: GIDL, Noise, RF and Negative Capacitance Effect 

M.Tech Thesis: Reliability Study of Low Voltage programmable Ultra-thin Tunnel Oxide FGMOS Gate Stack [Link]

Journal Papers:

1.  D Nandi, Chetan Kumar Dabhi, D Rajasekaran, N Karumuri, S Turuvekere, A Dutta, B Swaminathan, S Srihari, C Hu, and Y S Chauhan, “Nonlinear Body Resistance in SOI MOSFETs under Dynamic Depletion: Compact Modeling and DC Characterization”, IEEE Transactions on Electron Devices,, 2026, doi: 10.1109/TED.2026.3652538.

2. Chetan Kumar Dabhi, Girish Pahwa, Sayeef Salahuddin, Chenming Hu, "Boltzmann-Statistics Aware Non-Quasi-Static-Charge Model for IC Simulations", in IEEE Transactions on Electron Devices, vol. 72, no. 1, pp. 357-363, Jan. 2025.

3. Y. H. Zarkob, D. Rajasekharan, A. Pampori, A. Sharma, G. Pahwa, C. K. Dabhi, V. Kubrak, B. Peddenpohl, M. Tang, C. Hu, and Y. S. Chauhan, "Impact Ionization in LDMOS Transistors: Improved Compact Model and Asymmetry under Forward and Reverse Modes of Operation", IEEE Journal of the Electron Devices Society, 2025.

4. D. Nandi, C. K. Dabhi, D. Rajasekharan, N. Karumuri, S. Turuvekere, A. Dutta, B. Swaminathan, S. Srihari, C. Hu, Y. S. Chauhan, "Utilizing Symmetric BSIM-SOI SPICE model for Dynamically Depleted RF SOI T/R Switches and Logic Circuits", in, Journal of Electron Device Society, 2024 doi: 10.1109/JEDS.2024.3484295. 

5. D. Nandi, C. K. Dabhi, D. Rajasekharan, N. Karumuri, S. Turuvekere, S. Choppalli, A. S. Pratiyush, C. Hu, and Y. S. Chauhan, "Physical Insights and Accurate Modeling of Transconductance in Body-contacted Dynamically Depleted SOI MOSFETs", accepted in IEEE Transactions on Electron Devices, 2024.

6. C. T. Tung, C. K. Dabhi, S. Salahuddin, C. Hu, "A Versatile Compact Model of Resistive Random-Access Memory (RRAM)  ", accepted in Solid State Electronics, 2024.

7. C. T. Tung, A. Pampori, C. K. Dabhi, S. Salahuddin, C. Hu, "A Novel Neural Network-based Transistor Compact Model Including Self-Heating" accepted in the IEEE Electron Device Letters, 2024.

8. S. Chatterjee, S. Kumar, A. Gaidhane, C. K. Dabhi, Y. S. Chauhan, and H. Amrouch, "Temperature and Variability-Aware Compact Modeling of Ferroelectric FDSOI FET for Memory and Emerging Applications", Solid State Electronics, 2024. (Accepted)

9. A. Sharma, Y. Hayat, G. Pahwa, C. K. Dabhi, R. Goel, A. Agarwal, V. Kubrak, M. Tang, M. Treiber, C. Hu, Y.S. Chauhan, "Compact Modeling of Impact Ionization and Conductivity Modulation in LDMOS Transistors" accepted in IEEE Transactions on Electron Devices, 2024.

10. Chetan Kumar Dabhi, D. Rajasekharan, G. Pahwa, D. Nandi, N. Karumuri, S. Turuvekere, A. Dutta, B. Swaminathan, S. Srihari, Y. S. Chauhan, S. Salahuddin, C. Hu, "Symmetric BSIM-SOI—Part I: A Compact Model for Dynamically Depleted SOI MOSFETs" in, IEEE Transactions on Electron Devices, volume 71, number 4, pages 2284-2292, 2024.

11.  Chetan Kumar Dabhi, D. Nandi, K. Nandan, D. Rajasekharan, G. Pahwa, N. Karumuri, S. Turuvekere, A. Dutta, B. Swaminathan, S. Srihari, Y. S. Chauhan, S. Salahuddin, C. Hu, "Symmetric BSIM-SOI—Part II: A Compact Model for Partially Depleted SOI MOSFETs"  in, IEEE Transactions on Electron Devices,  vol. 71, no. 4, pp. 2293-2300, April 2024.

12. S. Kumar, S. Chatterjee, C. K. Dabhi, Y. S. Chauhan, and H. Amrouch, "Non-Traditional Design of Dynamic Logics using FDSOI for Ultra-Efficient Computing", IEEE Journal of Exploratory Solid-State Computational Devices and Circuits, vol. 9, no. 1, pp. 74-82, June 2023. 

13. S. Chatterjee, S. Kumar, A. Gaidhane, C. K. Dabhi, Y. S. Chauhan, and H. Amrouch, "Ferroelectric FDSOI FET Modeling for Memory and Logic Applications", Solid State Electronics, Volume 200, 2023.

14. Chetan Kumar Dabhi, A. S. Roy, L. Yang and Y. S. Chauhan, "Anomalous GIDL Effect with Back Bias in FinFET: Physical Insights and Compact Modeling", IEEE Transactions on Electron Devices vol. 68, no. 7, pp. 3261-3267, July 2021.

15. O. Prakash, G. Pahwa, C. K. Dabhi, Y. S. Chauhan, and H. Amrouch, "Impact of Self-Heating on Negative-Capacitance FinFET: Device-Circuit Interaction", IEEE Transactions on Electron Devices,  vol. 68, no. 4, pp. 1420-1424, April 2021.

16. Chetan Kumar Dabhi, S. S. Parihar, A. Dasgupta, and Y. S. Chauhan, "Compact Model of Negative-Capacitance FDSOI FETs for Circuit Simulations", IEEE Transactions on Electron Devices, vol. 67, no. 7, pp. 2710-2716, July 2020. [News]

17. F. Bellando, C. K. Dabhi, A. Saeidi, C. Gastaldi, Y. S. Chauhan, and A. M. Ionescu, "Subthermionic Negative Capacitance Ion Sensitive Field-Effect Transistor", Applied Physics Letters, 27 April 2020.  

18. H. Amrouch, G. Pahwa, A. D. Gaidhane, C. K. Dabhi, F. Klemme, O. Prakash and Y. S. Chauhan, "Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology", IEEE Transactions on Circuits and Systems I, vol. 67, no. 9, pp. 3127-3137, Sept. 2020. 

19. Chetan Kumar Dabhi, Ananda S. Roy, Yogesh S. Chauhan, "Compact Modeling of Temperature-Dependent Gate-Induced Drain Leakage Including Low-Field Effects", in "IEEE Transactions on Electron Devices " Vol. 66, Issue 7, Pages 2892-2897, 2019.

20. Chetan. K. Dabhi, A. Dasgupta, P. Kushwaha, H. Agarwal, C. Hu and Y. S. Chauhan, "Modeling of Induced Gate Thermal Noise Including Back-Bias Effect in FDSOI MOSFET," in IEEE Microwave and Wireless Components Letters, vol. 28, no. 7, pp. 597-599, July 2018.

21. Subrat Mishra, Hussam Amrouch, Jerin Joe, Chetan K Dabhi, Karansingh Thakor, Yogesh S Chauhan, Jörg Henkel, Souvik Mahapatra  "A Simulation Study of NBTI Impact on 14-nm Node FinFET Technology for Logic Applications: Device Degradation to Circuit-Level Interaction," in IEEE Transactions on Electron Devices, vol. 66, no. 1, pp. 271-278, Jan. 2019.

22. S. Mishra, N. Parihar, A. R, C. K. Dabhi, Y. S. Chauhan and S. Mahapatra, "NBTI-Related Variability Impact on 14-nm Node FinFET SRAM Performance and Static Power: Correlation to Time Zero Fluctuations," in IEEE Transactions on Electron Devices, vol. 65, no. 11, pp. 4846-4853, Nov. 2018.

23. A Thirunavukkarasu, Hussam Amrouch, Jerin Joe, Nilesh Goel, Narendra Parihar, Subrat Mishra, Chetan K Dabhi, Yogesh S Chauhan, Jörg Henkel, Souvik Mahapatra , "Device to Circuit Framework for Activity-Dependent NBTI Aging in Digital Circuits," in IEEE Transactions on Electron Devices, vol. 66, no. 1, pp. 316-323, Jan. 2019.

24. Chetan Dabhi, Ganesh C Patil , "Underlap channel silicon-on-insulator quantum dot floating-gate MOSFET for low-power memory applications", "Journal of Computational Electronics ", Volume 15, Issue 4, Pages 1563-1569, 2016.

25. Neha Barothiya,  Chetan Dabhi, Ganesh C. Patil, "A Novel Channel Engineered Continuous Floating Gate MOSFET for Memory Applications", "Journal of Nanoelectronics and Optoelectronics", Volume 14, Number 5,, pp. 606-613, May 2019.

Conference Papers:

1. D. Nandi, C. K. Dabhi, D. Rajasekharan, N. Karumuri, S. Turuvekere,S. S. Parihar, A. Pampori, A. Dutta, C. Hu, and Y. S. Chauhan, "Recent Enhancements in the Industry-Standard Surface Potential-Based BSIM-SOI Compact Model", International Compact Modeling Conference (ICMC), San Francisco, June 2025.

2. Y. H. Zarkob, M. S. Nazir, A. Naseer, A. Pampori, C. K. Dabhi, D. Rajasekharan, Z. Chaosong, L. S. Ee, C. Hu, and Y. S. Chauhan, "Characterization and Modeling of Flicker Noise in Bulk MOSFETs down to Sub-Threshold Regime", International Compact Modeling Conference (ICMC), San Francisco, June 2025.

3. D. Nandi, C. K. Dabhi, D. Rajasekharan, N. Karumuri, S. Turuvekere, S. Choppalli, A. Dutta, C. Hu, and Y. S. Chauhan, "Accurate Modeling of Sub-threshold region considering the impact of STI edge conduction in Surface potential-based BSIM-SOI Compact Model Framework", International Compact Modeling Conference (ICMC), San Francisco, June 2025.

4. D. Nandi, C. K. Dabhi, D. Rajasekaran,  N. Karumuri, S. Turuvekere, B. Swaminathan, S. Srihari, A. Dutta, C. Hu, and Y. S. Chauhan, "Validation of Dynamically Depleted Symmetric BSIM-SOI Compact model for RFSOI T/R Switch Applications,"  Bengaluru, India, Mar. 2024.

5. Y. H. Zarkob, A. Sharma, G. Pahwa, D. Nandi, C. K. Dabhi, V. Kubrak, B. Peddenpohl, M. Tang, C. Hu and Y. S. Chauhan, "Compact Modeling and Experimental Validation of Reverse Mode Impact Ionization in LDMOS Transistors within the BSIM-BULK Framework", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Bengaluru, India, Mar. 2024. 

6. G. Pahwa, A. Dasgupta, C. T. Tung, M.Y. Kao, C. K. Dabhi, S. Sarker, S. Salahuddin and C. Hu, "Compact Modeling of Emerging IC Devices for Technology-Design Co-development", IEEE International Electron Devices Meeting (IEDM), San Francisco, CA, USA, 2022, pp. 8.1.1-8.1.4, doi: 10.1109/IEDM45625.2022.10019433. (Invited)  

7. A. Sharma, Y. H. Zarkob, R. Goel, C. K. Dabhi, G. Pahwa, C. Hu, and Y. S. Chauhan, "Recent Enhancements in the Standard BSIM-BULK MOSFET Model", IEEE International Conference on Emerging Electronics (ICEE), Bangalore, India, 2022, pp. 1-6, doi: 10.1109/ICEE56203.2022.10118345. 

8. Chetan K. Dabhi, Girish Pahwa, Sayeef Salahuddin, and Chenming Hu, "Compact Model for Trap Assisted Tunneling based GIDL", Device Research Conference (DRC), Columbus, OH, USA, 2022, pp. 1-2, doi: 10.1109/DRC55272.2022.9855798. 

9. Swetaki Chatterjee, Shubham Kumar, Amol Gaidhane, Chetan K. Dabhi, Yogesh S. Chauhan, Hussam Amrouch, "Ferroelectric FDSOI FET Modeling for Memory and Logic Applications", International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Granada, Spain., Sept. 6-8 - 2022

10. S. Kumar, S. Chatterjee, C. K. Dabhi, H. Amrouch, and Y. S. Chauhan, "A Novel Approach to Mitigate Power Side-Channel Attacks for Emerging Negative Capacitance Transistor Technology", 20th IEEE International NEWCAS Conference, 2022, Quebec City, QC, Canada, 2022, pp. 504-508, doi: 10.1109/NEWCAS52662.2022.9842186.

11. S. Chatterjee, S. Kumar, A. D. Gaidhane, C. K. Dabhi, H. Amrouch, and Y. S. Chauhan, "Modeling of Fe-FDSOI FET for Memory and Neuromorphic Applications", DATE (Design, Automation and Test in Europe Conference) 2022 workshop on Ferroelectronics, Mar. 2022.

12. S. Kumar, S. Chatterjee, C. K. Dabhi, H. Amrouch, and Y. S. Chauhan, "Novel FDSOI-Based Dynamic XNOR Logic for Ultra-Efficient High-Dense Computing", IEEE International Symposium on Circuits & Systems (ISCAS), Austin, TX, USA, 2022, pp. 3373-3377, doi: 10.1109/ISCAS48785.2022.9937329. 

13. O. Prakash, C. K. Dabhi, Y. Chauhan, and H. Amrouch, "Transistor Self-Heating: The Rising Challenge for Semiconductor Testing", IEEE VLSI Test Symposium (VTS’21), San Diego, CA, USA, 2021, pp. 1-7, doi: 10.1109/VTS50974.2021.9441002. 

14. Chetan. K. Dabhi, P. Kushwaha, H. Agarwal, S. S. Chauhan, C. Hu, and Y. S. Chauhan, "Physical Analysis of Non-monotonic DIBL Dependence on Back Gate Bias in Thick Front Gate Oxide FDSOI MOSFETs", IEEE SOI–3D–Subthreshold Microelectronics Technology Unified Conference (S3S), San Jose, CA, USA, pp. 1-3, OCt 2019, doi: 10.1109/S3S46989.2019.9320666. 

15. V. Kumar, Chetan. K. Dabhi, S. Singh Parihar and Y. S. Chauhan, "Analysis and Compact Modeling of Drain-Extended FinFET," 2019 IEEE Conference on Modeling of Systems Circuits and Devices (MOS-AK India), Hyderabad, India, 2019, pp. 97-101. doi: 10.1109/MOS-AK.2019.8902458 

16. P. Kushwaha, H. Agarwal, Chetan. K. Dabhi, Y.-K. Lin, J. P. Duarte, C. Hu, and Y. S. Chauhan, "A Unified Flicker Noise Model for FDSOI MOSFETs Including Back-bias Effect", IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), Bengaluru, India, Mar. 2018, pp. 1-5, doi: 10.1109/CONECCT.2018.8482376. 

17. Chetan. K. Dabhi, P. Kushwaha, A. Dasgupta, H. Agarwal and Y. S. Chauhan, "Impact of back plane doping on RF performance of FD-SOI transistor," 2016 3rd International Conference on Emerging Electronics (ICEE), Mumbai, 2016, pp. 1-4. doi: 10.1109/ICEmElec.2016.8074584 

18. Chetan. K. Dabhi, A. Dasgupta and Y. S. Chauhan, "Computationally efficient analytical surface potential model for UTBB FD-SOI transistors," 2016 3rd International Conference on Emerging Electronics (ICEE), Mumbai, 2016, pp. 1-4. doi: 10.1109/ICEmElec.2016.8074575