Chetan Kumar Dabhi, PhD, Senior Member IEEE
Staff Engineer, Technology and Device Modeling-R&D Division, pSemi Corporation, San Diego | Former Postdoctoral Fellow at UC Berkeley (BSIM Group), Berkeley Device Modeling Center (BDMC) | PhD- IIT Kanpur | M.Tech-NIT Surat
Chetan Kumar Dabhi has served as an "Adjunct Assistant Professor" at NIT Nagpur, and received B. Tech from Shantilal Shah Eng. Collage, Bhavnagar University (Gujarat Technological University).
About my Skills and Research Area:
Throughout my career, I've concentrated on practical solutions involving device measurements in collaboration with the semiconductor industry. I'm known for quickly mastering new skills, comprehending complex mathematical concepts, and developing efficient test-driven EDA solutions. A natural leader and mentor.
Developed a Symmetric BSIM-SOI 100.1.0 model that is accurate, fast, and robust. Created new compact models for advanced node BSIM-CMG.
During my postdoctoral tenure with the BSIM Group at UC Berkeley, I specialize in developing and supporting industry-standard compact models for diverse semiconductor devices, including SOI FETs, FinFETs, and Bulk FETs (BSIM-SOI, BSIM-IMG, BSIM-BULK, and BSIM4). These models, integral to major commercial SPICE simulators, facilitate precise and efficient circuit design and simulation.
A notable accomplishment is the creation of the Dynamic Depletion SOI FETs BSIM compact model tailored for RF designs/PDK. This model is now incorporated into widely used commercial circuit simulators such as HSPICE, ADS, Spectre, AFS, and more.
Armed with a Ph.D. in Microelectronics from IIT Kanpur, my doctoral research delved into physics-based leakage modeling and negative capacitance modeling for advanced technology nodes like FinFET, UTBB-FDSOI, and GAA. I've contributed to more than 35 publications in IEEE journals and conferences, focusing on enhancing FinFET/GAA, SOI, BULK FET modeling. My research interests encompass alternative device structures, physics, and materials for deeply scaled CMOS, along with compact modeling of semiconductor devices.
