Chetan Kumar Dabhi, PhD
Postdoctoral Fellow at UC Berkeley (BSIM Group), Berkeley Device Modeling Center (BDMC)
PhD- IIT Kanpur | M.Tech-NIT Surat
Chetan Kumar Dabhi has served as an "Adjunct Assistant Professor" at NIT Nagpur, and received B. Tech from Shantilal Shah Eng. Collage, Bhavnagar University (Gujarat Technological University).
About my Skills and Research Area:
Throughout my career, I've concentrated on practical solutions involving device measurements in collaboration with the semiconductor industry. I'm known for quickly mastering new skills, comprehending complex mathematical concepts, and developing efficient test-driven EDA solutions. A natural leader and mentor.
Developed a Symmetric BSIM-SOI 100.1.0 model that is accurate, fast, and robust. Created new compact models for advanced node BSIM-CMG.
During my postdoctoral tenure with the BSIM Group at UC Berkeley, I specialize in developing and supporting industry-standard compact models for diverse semiconductor devices, including SOI FETs, FinFETs, and Bulk FETs (BSIM-SOI, BSIM-IMG, BSIM-BULK, and BSIM4). These models, integral to major commercial SPICE simulators, facilitate precise and efficient circuit design and simulation.
A notable accomplishment is the creation of the Dynamic Depletion SOI FETs BSIM compact model tailored for RF designs/PDK. This model is now incorporated into widely used commercial circuit simulators such as HSPICE, ADS, Spectre, AFS, and more.
Armed with a Ph.D. in Microelectronics from IIT Kanpur, my doctoral research delved into physics-based leakage modeling and negative capacitance modeling for advanced technology nodes like FinFET, UTBB-FDSOI, and GAA. I've contributed to more than 30 publications in IEEE journals and conferences, focusing on enhancing FinFET/GAA, SOI, BULK FET modeling. My research interests encompass alternative device structures, physics, and materials for deeply scaled CMOS, along with compact modeling of semiconductor devices.
News:
1. Simulation Tool: BSIM Group's new compact model on dynamically depleted SOI FETs (Symmetric BSIM-SOI) is now accessible in commercial simulators such as HSPICE, Spectre, and ADS (Core developer & project leader - C. K. Dabhi): BSIM-SOI 100.0.0, 100.0.1 and 100.1.0.
1. C. K. Dabhi, D. Rajasekharan, G. Pahwa, D. Nandi, N. Karumuri, S. Turuvekere, A. Dutta, B. Swaminathan, S. Srihari, Y. S. Chauhan, S. Salahuddin, C. Hu,
"Symmetric BSIM-SOI – Part I: A Compact Model for Dynamically Depleted SOI MOSFETs", in IEEE Transactions on Electron Devices, doi: 10.1109/TED.2024.3363110.
2. C. K. Dabhi, D. Nandi, K. Nandan, D. Rajasekharan, G. Pahwa, N. Karumuri, S. Turuvekere, A. Dutta, B. Swaminathan, S. Srihari, Y. S. Chauhan, S. Salahuddin, C. Hu, "Symmetric BSIM-SOI – Part II: A Compact Model for Partially Depleted SOI MOSFETs", in IEEE Transactions on Electron Devices, doi: 10.1109/TED.2024.3363117
The BSIM-SOI 100.1.0 model is in the public domain and the code can be downloaded using the following links
1. https://si2.org/download-links/
2. https://bsim.berkeley.edu/models/bsimsoi/ (If the download error occurs, attempt to use the default browser on your machine)
2. IEEE EDL Goldel list of reviewers -2022-23
3. IEEE TED Goldel list of reviewers -2018-23
Research Area:
FinFET: Unified GIDL Model for Advance Technology nodes & Variability modeling (BSIM-CMG)
Compact Modeling of Negative Capacitance FET: Self-heating Effect & Variability Modeling (BSIM-CMG)
Compact Modeling: Device Degradation (NBTI) to Circuit Frame Work (BSIM-CMG)
FD-SOI: Compact Modeling of Negative Capacitance FET (BSIM-IMG)
FD-SOI: RF Modeling of Fully Depleted Silicon on Insulator FET (BSIM-IMG)
Symmetric BSIM-SOI model (Dynamic Depletion model) for RF PDKs (CMC & BDMC)
Recent Updates:
1. Dec. 2021: Delivered talk on Improved NQS Modeling at Industry Advisory Board Meeting, Berkeley Device Modeling Center (BDMC), UC Berkeley.
2. Sept. 2021: Delivered talk on GIDL compact model at advanced technology nodes, Berkeley Device Modeling Center (BDMC), UC Berkeley.
3. Feb 2021: Our recent paper on the unified GIDL model for advanced technology nodes has been accepted in IEEE TED, 2021.
4. April 2020: First experimental demonstration of NC-ISFET and Modeling:
5. July 2020: paper titled "Compact Modeling of Negative-Capacitance FDSOI FETs for Circuit Simulations" accepted for publication in IEEE Transactions on Electronics Devices. #NC-FDSOI #UTBBFDSOI
6. June 2019: Invited Talk: "BSIM-IMG: Industry Standard Model with Fast and Extended Range Core Including Improved Mobility and Noise models ", MOS-AK, June 20-22, 2019, Chengdu, China