Many-core system-on-chip (SoC) architecture and design challenges and opportunities spanning edge devices to cloud computing systems in scaled CMOS process are presented. Key techniques for robust and variation-tolerant logic, embedded memory arrays and on-die interconnect fabrics are discussed. Fine-grain multi-voltage design and power management techniques, featuring integrated voltage regulators for wide dynamic voltage-frequency operating range and flexible platform power control across multi-threaded high-throughput near-threshold voltage (NTV) to single-threaded burst performance modes, are elucidated. Smart variation-aware workload mapping, runtime self-adaptation and error detection and recovery schemes to mitigate impacts of process-voltage-temperature (PVT) variations and aging, and achieve maximum performance under stringent thermal and energy constraints, are presented. Latest advances in design and process/package for realization of monolithic and heterogeneous 2D/3D-integrated compact, efficient, low supply noise, fine-grain, high-bandwidth and fast-response power converters and voltage regulators, essential for implementing intelligent system-level power management and adaptation schemes across hardware and software, are also highlighted. Real SoC examples are used to demonstrate leading-edge practical systems.

Speaker Bio:  

Dr. Vivek De (F’11) received the B.Tech. degree from IIT Madras, Chennai, India, the M.S. degree from Duke University, Durham, NC, USA, and the Ph.D. degree from the Rensselaer Polytechnic Institute, Troy, NY, USA, all in electrical engineering. 

He is an Intel Fellow and the Circuit Technology Research Director at Intel Labs, Hillsboro, OR, USA. He is responsible for leading and inspiring long-term research in future circuit technologies and design techniques for system-on-chip (SoC) designs focusing on energy efficiency. He has published 350 papers in refereed international conferences and journals with a citation H-index of 86 and has 241 patents issued with 25 more patents filed (pending).

Dr. De was a recipient of the 2019 IEEE Circuits and System Society (CASS) Charles A. Desoer Technical Achievement Award for pioneering contributions to leading-edge performance and energy-efficient microprocessors & many-core system-on-chip (SoC) designs and the 2020 IEEE Solid-State Circuits Society (SSCS) Industry Impact Award for seminal impact and distinctive contributions to the field of solid-state circuits and the integrated circuits industry. He received the Outstanding Evening Session Award from the 2018 International Solid-State Circuits Conference (ISSCC), the 2017 Distinguished Alumnus Award from IIT Madras, the Intel Achievement Award for his contributions to an integrated voltage regulator technology, the Best Paper Award from the 1996 IEEE International ASIC Conference, and nominations for Best Paper Awards from the 2007 IEEE/ACM Design Automation Conference (DAC) and the 2008 IEEE/ACM International Conference on Computer-Aided Design (ICCAD). He co-authored a paper nominated for the Best Student Paper Award at the 2017 IEEE International Electron Devices Meeting (IEDM). One of his publications was recognized at the 2013 IEEE/ACM Design Automation Conference (DAC) as one of the “Top 10 Cited Papers in 50 Years of DAC.” Another one of his publications received the Most Frequently Cited Paper Award from the IEEE Symposium on VLSI Circuits at its 30th Anniversary in 2017. He was recognized as a Top 10 Contributor to the IEEE International Solid-State Circuits Conference (ISSCC) at its 70th Anniversary in 2023, a Prolific Contributor at its 60th Anniversary in 2013, and a Top 10 Contributor to the IEEE Symposium on VLSI Circuits at its 30th Anniversary in 2017. He served as an IEEE/EDS Distinguished Lecturer in 2011, an IEEE/SSCS Distinguished Lecturer from 2017 to 2018, and an IEEE/CASS Distinguished Lecturer from 2020 to 2022.