With continued scaling, the reliability issues cause an increasing failure of nanometer-scale analog/mixed-signal (AMS) VLSI. For example, the significantly increased sensitivity to aging-associated wear-out phenomena causes the shifting of electrical signals from their nominal values. Overheat temperatures bring thermal noise interference. However, traditional simulations are computationally expensive. Besides, the verification-then-fix approaches cause low efficiency of design and verification. Recently, machine learning (ML) techniques have achieved impressive success in various applications. In this talk, we will present our research about ML in AMS VLSI design for reliability to improve the efficiency of verification and design closure.

 Speaker Bio:  

Prof. Tinghuan CHEN is an Assistant Professor at the Chinese University of Hong Kong, Shenzhen. Previously, he was a post-doctoral fellow at ACCESS, CUHK and TUM. He earned his Ph.D. from CUHK, advised by Prof. Bei YU. His research interests include machine learning in EDA and deep learning accelerators. He has published 26 papers, including 7 top-tier conference/journal papers (e.g., DAC, TCAD and ICCV), 5 high-rank conference/journal papers (e.g., ICCAD, DATE and TNNLS), and 1 ESI Highly Cited Paper. He has served as a program committee member in AAAI (2023), MLCAD (2023) and IJCAI (2021-2023).